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Data Sheet
S6E63D6
Preliminary
240 RGB X 320 Dot 1-Chip Driver IC with LTPS Interface for 262,144 Color AMOLED Display Panel
November 7, 2006
System LSI Division Device Solution Network SAMSUNG ELECTRONICS CO., LTD. (http://www.samsung.com/Products/Semiconductor/DisplayDriverIC)
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary CONTENTS
ALIGN KEY CONFIGURATION AND COORDINATE ......................................................................................10 POWER SUPPLY PINS ....................................................................................................................................15 SYSTEM / RGB INTERFACE PINS..................................................................................................................17 DISPLAY PINS..................................................................................................................................................20 MISCELLANEOUS PINS ..................................................................................................................................20 SYSTEM INTERFACE ......................................................................................................................................21 HIGH SPEED SERIAL INTERFACE (MDDI) ....................................................................................................22 SUB PANEL CONTROL....................................................................................................................................22 EXTERNAL INTERFACE (RGB-I/F) .................................................................................................................22 ADDRESS COUNTER (AC)..............................................................................................................................22 GRAPHICS RAM (GRAM) ................................................................................................................................22 TIMING GENERATOR ......................................................................................................................................22 GRAYSCALE VOLTAGE GENERATOR ..........................................................................................................22 OSCILLATION CIRCUIT (OSC)........................................................................................................................22 SOURCE DRIVER CIRCUIT.............................................................................................................................23 LTPS PANEL INTERFACE CIRCUIT ...............................................................................................................23 GRAM ADDRESS MAP ....................................................................................................................................24 INSTRUCTION TABLE .....................................................................................................................................27 Index ..........................................................................................................................................................30 Status Read ...............................................................................................................................................30 No Operation (R00h) .................................................................................................................................30 STAND BY (R10h).....................................................................................................................................47 POWER GEN1 (R12h) ..............................................................................................................................48 POWER GEN2 (R13h) ..............................................................................................................................49 POWER STEP UP CONTROL 1 (R14h) ...................................................................................................51 START OSCILLATION (R18h) ..................................................................................................................52 SOURCE DRIVER CONTROL (R1Ah)......................................................................................................53 WRITE DATA TO GRAM (R22h)...............................................................................................................55 READ DATA FROM GRAM (R22h)...........................................................................................................56 SELECT DATA BUS 1 (R23h)...................................................................................................................57 SELECT DATA BUS 2 (R24h)...................................................................................................................57 VERTICAL SCROLL CONTROL 1 (R30h, R31h) .....................................................................................58 VERTICAL SCROLL CONTROL 2 (R32h) ................................................................................................59 PARTIAL SCREEN DRIVING POSITION (R33h, R34h)...........................................................................61 RESTRICTION ON PARTIAL DISPLAY AREA SETTING ........................................................................62 [NOTE] 000h SS18 to 10 SE18 to 10 13Fh......................................................................................62 VERTICAL RAM ADDRESS POSITION (R35h,R36h)..............................................................................63 HORIZONTAL RAM ADDRESS POSITION (R37h)..................................................................................63 CLIENT INITIATED WAKE-UP (R38h)......................................................................................................64 MDDI LINK WAKE-UP START POSITION (R39h) ...................................................................................64 SUB PANEL CONTROL 1 (R3Ah / R3Bh) ................................................................................................64 SUB PANEL CONTROL 2 (R3Ch) ............................................................................................................65 TEST KEY COMMAND (R60h) .................................................................................................................66 MTP CONTROL (R61h) ............................................................................................................................66 MTP REGISTER SETTING (R62h, R63h, R64h, R65h) ...........................................................................66 GPIO CONTROL (R66h/R67h/R68h/R69h/R6Ah) ....................................................................................71 GAMMA CONTROL (R70h to R78h).........................................................................................................72
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
INSTRUCTION SET INITIALIZATION .............................................................................................................. 73 PATTERN DIAGRAMS FOR VOLTAGE SETTING.......................................................................................... 74 VOLTAGE REGULATION FUNCTION ............................................................................................................. 75 SYSTEM INTERFACE...................................................................................................................................... 77 68-SYSTEM 18-BIT BUS INTERFACE..................................................................................................... 79 68-SYSTEM 16-BIT BUS INTERFACE..................................................................................................... 80 68-SYSTEM 9-BIT BUS INTERFACE....................................................................................................... 81 68-SYSTEM 8-BIT BUS INTERFACE....................................................................................................... 82 80-SYSTEM 18-BIT BUS INTERFACE..................................................................................................... 83 80-SYSTEM 16-BIT BUS INTERFACE..................................................................................................... 84 80-SYSTEM 9-BIT BUS INTERFACE....................................................................................................... 85 80-SYSTEM 8-BIT BUS INTERFACE....................................................................................................... 86 68-/80-SYSTEM 8-/9-BIT INTERFACE SYNCHRONIZATION FUNCTION ............................................. 87 SERIAL PERIPHERAL INTERFACE ........................................................................................................ 88 INDEX AND PARAMETER RECOGNITION............................................................................................. 90 18-Bit RGB interface ................................................................................................................................. 92 16-Bit RGB interface ................................................................................................................................. 92 6-Bit RGB interface ................................................................................................................................... 93 USAGE ON EXTERNAL DISPLAY INTERFACE ............................................................................................. 96 INTRODUCTION OF MDDI .............................................................................................................................. 97 DATA-STB ENCODING.................................................................................................................................... 97 MDDI DATA / STB ............................................................................................................................................ 98 HIBERNATION / WAKE-UP.............................................................................................................................. 99 MDDI LINK WAKE-UP PROCEDURE ............................................................................................................ 100 1) Host-initiated Link Wake-up Procedure .............................................................................................. 102 VSYNC Based Link Wake-up.................................................................................................................. 105 GPIO Based Link Wake-up ..................................................................................................................... 106 GPIO CONTROL............................................................................................................................................. 108 MDDI PACKET................................................................................................................................................ 111 Sub-frame header packet........................................................................................................................ 111 Register access packet ........................................................................................................................... 112 Video Stream packet ............................................................................................................................... 112 Filler packet ............................................................................................................................................. 113 Link shutdown packet.............................................................................................................................. 113 TEARING-LESS DISPLAY ............................................................................................................................. 116 1. 1. Display speed is faster than data write........................................................................................ 116 2. Display speed is slower than data write. ............................................................................................. 116 MAIN / SUB PANEL SELECTION .................................................................................................................. 118 SUB PANEL CONTROL TIMING.................................................................................................................... 119 1. TFT type sub panel timing................................................................................................................... 119 1.1 Register data transfer timing ............................................................................................................. 119 1.2 Video data transfer timing ................................................................................................................. 120 2. STN type sub panel timing .................................................................................................................. 123 2.1 Register data transfer timing ............................................................................................................. 123 2.2 Video data transfer timing ................................................................................................................. 124 SUB PANEL CONTROL TIMING.................................................................................................................... 125 1. Index/parameter write for sub panel LDI ............................................................................................. 125 2. Image data write for sub panel LDI ..................................................................................................... 125 3. Change data path from sub panel to main panel ................................................................................ 125 ABSOLUTE MAXIMUM RATINGS ................................................................................................................. 143
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DC CHARACTERISTICS ................................................................................................................................144 AC CHARACTERISTICS ................................................................................................................................149 RESET TIMING...............................................................................................................................................153 EXTERNAL POWER ON / OFF SEQUENCE.................................................................................................154 NOTICE ...........................................................................................................................................................155
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary INTRODUCTION
The S6E63D6 is a single chip solution for Gate-IC-less AMOLED panel. Source driver with built-in memory, gate-IC-less level shifter and power circuits are integrated on this LSI. It can display to the maximum of 240-RGB x 320-dot graphics on 260k-color AMOLED panel. Moreover, the chip supports LTPS panel. The S6E63D6 supports Qualcomm's high-speed serial interface, MDDI (Mobile Display Digital Interface) type I, which is an implementation of client device Video Electronics Standards Association (VESA) standard. The MDDI is a cost-effective low-power solution that enables high-speed short-range communication with a display device using a digital packet data link. The S6E63D6 also supports 18-/16-/9-/8-bit high-speed bus interface to enable efficient data transfer to the GRAM. There is an external interface. In case of display data, the S6E63D6 offers a flexible 18-/16-/6-bits bus of RGB interface for transferring the 260k colors display data. The motion picture area can be designated in GRAM by window function. The specified window area can be updated selectively so that motion picture can be displayed simultaneously independent of still picture area. The LSI operates at low voltage and has internal GRAMs to store 240-RGB x 320-dot 260k-color image data. Additionally, it has an internal booster that generates the OLED driving voltage and the voltage follower circuit for OLED driver. The S6E63D6 is suitable for any medium-sized or small portable mobile solution requiring long-term driving capabilities such as digital cellular phones supporting a web browser, bi-directional pagers, PMP, MP3P and small PDAs.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary FEATURES
Overalls - 240-RGBx320-dot AM-OLED display controller/driver IC for 262,144 colors - Gate IC less - 240 channel source driver with time shared driving function Various color-display control functions - 262,144 colors can be displayed at the same time with RGB separated gamma adjust. - 262,144 / 65,536/ 8 colors can be displayed. - Vertical scroll display function in line units Various interfaces - 18-/16-/9-/8-bit high-speed parallel bus interface (80- and 68- system) - Serial peripheral interface (SPI) - 18-/16-/6-bit RGB interface - MDDI (Mobile Display Digital Interface) support Internal ram capacity: 240 x 18 x 320 = 1,382,400 bits Writing to a window-ram address area by using a window-address function Efficiently panel driving signals SOUT[1:240] : V0~V63 grayscale FLM, SFTCLK, SFTCLKB, SCLK1, SCLK2, CLA, CLB, CLC, BICTL_L, BICTL_R, EX_FLM, EX_CLK, EX_CLKB, ESR : VGL to VGH level Low-power operation supports: - Power-save mode: standby mode - Partial display mode in any position Internal oscillation circuit and external hardware reset Internal power supply circuit Operating voltage * Apply voltage - I/O power-supply VDD3 to VSS = 1.65 to 3.3V - Analog power-supply VCI to VSS = 2.5 to 3.3V * Generated voltage - VGH = 4.6 to 6.6V (gate circuit power supply) - VGL = -7.8 to -5.0V (gate circuit power supply) - VINT = - 4.0 to -1.0V (OLED pixel initialization first power supply) - Source output range = 0.96 to 4.2V Released package type - S6E63D6 is released COG type package format only. - -
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary BLOCK DIAGRAM
Figure1: S6E63D6 Block Diagram
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary PAD CONFIGURATION
Figure2: Pad Configuration
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table1: S6E63D6 Pad Dimensions Items Chip size (With scribe lane; 80um) Chip thickness Bump pitch Pad name. Input pad Output pad Input pad (1-251) Output pad (264-539) Output pad (252-263, 540-551) All PADs 30 36 91 15 3 Size X 15,580 300 60 54 91 91 36 um Y 1,330 Unit
Pad size
Bump Height
Pitch OUTPUT BUMP
Y
X PITCH
Y
X
INPUT BUMP
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
ALIGN KEY CONFIGURATION AND COORDINATE
Figure3: COG Align Key
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary PAD CENTER COORDINATES
Table2: Pad Center Coordinates [Unit: um]
NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NAME DUMMY MTPG MTPD VCI VCI VCI VCI VCI VCI1 VCI1 VCI1 VCI1 VCI1 VSSC VSSC VSSC VSSC VSSC VSSC C12M C12M C12M C12P C12P C12P C11M C11M C11M C11P C11P C11P VLOUT1 VLOUT1 VLOUT1 VLOUT1 VLOUT1 VLOUT1 VLIN1 VLIN1 VLIN1 VLIN1 VLIN1 VLIN1 C31P C31P C31P C31M C31M C31M C32P X -7500.0 -7440.0 -7380.0 -7320.0 -7260.0 -7200.0 -7140.0 -7080.0 -7020.0 -6960.0 -6900.0 -6840.0 -6780.0 -6720.0 -6660.0 -6600.0 -6540.0 -6480.0 -6420.0 -6360.0 -6300.0 -6240.0 -6180.0 -6120.0 -6060.0 -6000.0 -5940.0 -5880.0 -5820.0 -5760.0 -5700.0 -5640.0 -5580.0 -5520.0 -5460.0 -5400.0 -5340.0 -5280.0 -5220.0 -5160.0 -5100.0 -5040.0 -4980.0 -4920.0 -4860.0 -4800.0 -4740.0 -4680.0 -4620.0 -4560.0 Y -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 NO 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME C32P C32P DUMMYL3 DUMMYL2 DUMMYL1 C32M C32M C32M VLOUT3 VLOUT3 VLOUT3 VLOUT3 VLOUT3 VLIN3 VLIN3 VLIN3 VLIN3 VLIN3 DUMMY DUMMY VLIN2 VLIN2 VLIN2 VLIN2 VLIN2 VLOUT2 VLOUT2 VLOUT2 VLOUT2 VLOUT2 C21P C21P C21P DUMMY DUMMY C21M C21M C21M V0 V0 V63 V63 VGS VGS VSSA VSSA VSSA VSSA VSSA VSSA X -4500.0 -4440.0 -4380.0 -4320.0 -4260.0 -4200.0 -4140.0 -4080.0 -4020.0 -3960.0 -3900.0 -3840.0 -3780.0 -3720.0 -3660.0 -3600.0 -3540.0 -3480.0 -3420.0 -3360.0 -3300.0 -3240.0 -3180.0 -3120.0 -3060.0 -3000.0 -2940.0 -2880.0 -2820.0 -2760.0 -2700.0 -2640.0 -2580.0 -2520.0 -2460.0 -2400.0 -2340.0 -2280.0 -2220.0 -2160.0 -2100.0 -2040.0 -1980.0 -1920.0 -1860.0 -1800.0 -1740.0 -1680.0 -1620.0 -1560.0 Y -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 NO 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 NAME VSSA VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RTEST VSS_MDDI VSS_MDDI VSS_MDDI VSS_MDDI MDP MDP MDP MDN MDN MDN MSP MSP MSP MSN MSN MSN VCI_MDDI VCI_MDDI VCI_MDDI VCI_MDDI Vtest Vtest VDD3 VDD3 VDD3 VDD3 VDD3 FUSE_EN S_PB VSSDUM ID_MIB VDD3DUM MDDI_EN TEST_MODE[1] TEST_MODE[0] X -1500.0 -1440.0 -1380.0 -1320.0 -1260.0 -1200.0 -1140.0 -1080.0 -1020.0 -960.0 -900.0 -840.0 -780.0 -720.0 -660.0 -600.0 -540.0 -480.0 -420.0 -360.0 -300.0 -240.0 -180.0 -120.0 -60.0 0.0 60.0 120.0 180.0 240.0 300.0 360.0 420.0 480.0 540.0 600.0 660.0 720.0 780.0 840.0 900.0 960.0 1020.0 1080.0 1140.0 1200.0 1260.0 1320.0 1380.0 1440.0 Y -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table3: Pad Center Coordinates (continued) [Unit: um]
NO 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 NAME EXCLK EN_EXCLK TEST_IN[6] TEST_IN[5] TEST_IN[4] TEST_IN[3] TEST_IN[2] TEST_IN[1] TEST_IN[0] VSSDUM DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 VSSDUM DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSSDUM VSYNC HSYNC DOTCLK ENABLE SDI SDO CSB RW_WRB RS VDD3DUM E_RDB RESETB TE TEST_OUT[2] TEST_OUT[1] TEST_OUT[0] VDD VDD VDD VDD X 1500.0 1560.0 1620.0 1680.0 1740.0 1800.0 1860.0 1920.0 1980.0 2040.0 2100.0 2160.0 2220.0 2280.0 2340.0 2400.0 2460.0 2520.0 2580.0 2640.0 2700.0 2760.0 2820.0 2880.0 2940.0 3000.0 3060.0 3120.0 3180.0 3240.0 3300.0 3360.0 3420.0 3480.0 3540.0 3600.0 3660.0 3720.0 3780.0 3840.0 3900.0 3960.0 4020.0 4080.0 4140.0 4200.0 4260.0 4320.0 4380.0 4440.0 Y -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 NO 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 NAME MVDD MVDD MVDD MVDD RVDD RVDD RVDD RVDD DUMMY VSP VSP VSP VSP VREG1OUT VREG1OUT VREG1OUT VREG1OUT VCI VCI VCI VCI VCI VCIRIN DUMMYR3 DUMMYR2 DUMMYR1 VGH VGH VGH VGH VGH DUMMY VGL VGL VGL VGL VGL VINT VINT VINT VINT VINT VINT VINT DUMMY EL_ON ELVDD ELVDD ELVDD ELVDD X 4500.0 4560.0 4620.0 4680.0 4740.0 4800.0 4860.0 4920.0 4980.0 5040.0 5100.0 5160.0 5220.0 5280.0 5340.0 5400.0 5460.0 5520.0 5580.0 5640.0 5700.0 5760.0 5820.0 5880.0 5940.0 6000.0 6060.0 6120.0 6180.0 6240.0 6300.0 6360.0 6420.0 6480.0 6540.0 6600.0 6660.0 6720.0 6780.0 6840.0 6900.0 6960.0 7020.0 7080.0 7140.0 7200.0 7260.0 7320.0 7380.0 7440.0 Y -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 -572.5 NO 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 NAME DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY EX_FLM EX_FLM EX_CLKB EX_CLKB EX_CLK EX_CLK BICTL_R BICTL_R ESR ESR CLA CLA CLB CLB CLC CLC DUMMY DUMMY SOUT_DUM1 SOUT[1] SOUT[2] SOUT[3] SOUT[4] SOUT[5] SOUT[6] SOUT[7] SOUT[8] SOUT[9] SOUT[10] SOUT[11] SOUT[12] SOUT[13] SOUT[14] SOUT[15] SOUT[16] SOUT[17] X 7500.0 7697.5 7697.5 7697.5 7697.5 7697.5 7697.5 7697.5 7697.5 7697.5 7697.5 7697.5 7697.5 7425.0 7371.0 7317.0 7263.0 7209.0 7155.0 7101.0 7047.0 6993.0 6939.0 6885.0 6831.0 6777.0 6723.0 6669.0 6615.0 6561.0 6507.0 6453.0 6399.0 6345.0 6291.0 6237.0 6183.0 6129.0 6075.0 6021.0 5967.0 5913.0 5859.0 5805.0 5751.0 5697.0 5643.0 5589.0 5535.0 5481.0 Y -572.5 -296.0 -242.0 -188.0 -134.0 -80.0 -26.0 28.0 82.0 136.0 190.0 244.0 298.0 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table4: Pad Center Coordinates (continued) [Unit: um]
NO 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 NAME SOUT[18] SOUT[19] SOUT[20] SOUT[21] SOUT[22] SOUT[23] SOUT[24] SOUT[25] SOUT[26] SOUT[27] SOUT[28] SOUT[29] SOUT[30] SOUT[31] SOUT[32] SOUT[33] SOUT[34] SOUT[35] SOUT[36] SOUT[37] SOUT[38] SOUT[39] SOUT[40] SOUT[41] SOUT[42] SOUT[43] SOUT[44] SOUT[45] SOUT[46] SOUT[47] SOUT[48] SOUT[49] SOUT[50] SOUT[51] SOUT[52] SOUT[53] SOUT[54] SOUT[55] SOUT[56] SOUT[57] SOUT[58] SOUT[59] SOUT[60] SOUT[61] SOUT[62] SOUT[63] SOUT[64] SOUT[65] SOUT[66] SOUT[67] X 5427.0 5373.0 5319.0 5265.0 5211.0 5157.0 5103.0 5049.0 4995.0 4941.0 4887.0 4833.0 4779.0 4725.0 4671.0 4617.0 4563.0 4509.0 4455.0 4401.0 4347.0 4293.0 4239.0 4185.0 4131.0 4077.0 4023.0 3969.0 3915.0 3861.0 3807.0 3753.0 3699.0 3645.0 3591.0 3537.0 3483.0 3429.0 3375.0 3321.0 3267.0 3213.0 3159.0 3105.0 3051.0 2997.0 2943.0 2889.0 2835.0 2781.0 Y 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 NO 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 NAME SOUT[68] SOUT[69] SOUT[70] SOUT[71] SOUT[72] SOUT[73] SOUT[74] SOUT[75] SOUT[76] SOUT[77] SOUT[78] SOUT[79] SOUT[80] SOUT[81] SOUT[82] SOUT[83] SOUT[84] SOUT[85] SOUT[86] SOUT[87] SOUT[88] SOUT[89] SOUT[90] SOUT[91] SOUT[92] SOUT[93] SOUT[94] SOUT[95] SOUT[96] SOUT[97] SOUT[98] SOUT[99] SOUT[100] SOUT[101] SOUT[102] SOUT[103] SOUT[104] SOUT[105] SOUT[106] SOUT[107] SOUT[108] SOUT[109] SOUT[110] SOUT[111] SOUT[112] SOUT[113] SOUT[114] SOUT[115] SOUT[116] SOUT[117] X 2727.0 2673.0 2619.0 2565.0 2511.0 2457.0 2403.0 2349.0 2295.0 2241.0 2187.0 2133.0 2079.0 2025.0 1971.0 1917.0 1863.0 1809.0 1755.0 1701.0 1647.0 1593.0 1539.0 1485.0 1431.0 1377.0 1323.0 1269.0 1215.0 1161.0 1107.0 1053.0 999.0 945.0 891.0 837.0 783.0 729.0 675.0 621.0 567.0 513.0 459.0 405.0 351.0 297.0 243.0 189.0 135.0 81.0 Y 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 NO 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 NAME SOUT[118] SOUT[119] SOUT[120] SOUT[121] SOUT[122] SOUT[123] SOUT[124] SOUT[125] SOUT[126] SOUT[127] SOUT[128] SOUT[129] SOUT[130] SOUT[131] SOUT[132] SOUT[133] SOUT[134] SOUT[135] SOUT[136] SOUT[137] SOUT[138] SOUT[139] SOUT[140] SOUT[141] SOUT[142] SOUT[143] SOUT[144] SOUT[145] SOUT[146] SOUT[147] SOUT[148] SOUT[149] SOUT[150] SOUT[151] SOUT[152] SOUT[153] SOUT[154] SOUT[155] SOUT[156] SOUT[157] SOUT[158] SOUT[159] SOUT[160] SOUT[161] SOUT[162] SOUT[163] SOUT[164] SOUT[165] SOUT[166] SOUT[167] X 27.0 -27.0 -81.0 -135.0 -189.0 -243.0 -297.0 -351.0 -405.0 -459.0 -513.0 -567.0 -621.0 -675.0 -729.0 -783.0 -837.0 -891.0 -945.0 -999.0 -1053.0 -1107.0 -1161.0 -1215.0 -1269.0 -1323.0 -1377.0 -1431.0 -1485.0 -1539.0 -1593.0 -1647.0 -1701.0 -1755.0 -1809.0 -1863.0 -1917.0 -1971.0 -2025.0 -2079.0 -2133.0 -2187.0 -2241.0 -2295.0 -2349.0 -2403.0 -2457.0 -2511.0 -2565.0 -2619.0 Y 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5
13
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table5: Pad Center Coordinates (continued) [Unit: um]
NO 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 NAME SOUT[168] SOUT[169] SOUT[170] SOUT[171] SOUT[172] SOUT[173] SOUT[174] SOUT[175] SOUT[176] SOUT[177] SOUT[178] SOUT[179] SOUT[180] SOUT[181] SOUT[182] SOUT[183] SOUT[184] SOUT[185] SOUT[186] SOUT[187] SOUT[188] SOUT[189] SOUT[190] SOUT[191] SOUT[192] SOUT[193] SOUT[194] SOUT[195] SOUT[196] SOUT[197] SOUT[198] SOUT[199] SOUT[200] SOUT[201] SOUT[202] SOUT[203] SOUT[204] SOUT[205] SOUT[206] SOUT[207] SOUT[208] SOUT[209] SOUT[210] SOUT[211] SOUT[212] SOUT[213] SOUT[214] SOUT[215] SOUT[216] SOUT[217] X -2673.0 -2727.0 -2781.0 -2835.0 -2889.0 -2943.0 -2997.0 -3051.0 -3105.0 -3159.0 -3213.0 -3267.0 -3321.0 -3375.0 -3429.0 -3483.0 -3537.0 -3591.0 -3645.0 -3699.0 -3753.0 -3807.0 -3861.0 -3915.0 -3969.0 -4023.0 -4077.0 -4131.0 -4185.0 -4239.0 -4293.0 -4347.0 -4401.0 -4455.0 -4509.0 -4563.0 -4617.0 -4671.0 -4725.0 -4779.0 -4833.0 -4887.0 -4941.0 -4995.0 -5049.0 -5103.0 -5157.0 -5211.0 -5265.0 -5319.0 Y 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 NO 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 NAME SOUT[218] SOUT[219] SOUT[220] SOUT[221] SOUT[222] SOUT[223] SOUT[224] SOUT[225] SOUT[226] SOUT[227] SOUT[228] SOUT[229] SOUT[230] SOUT[231] SOUT[232] SOUT[233] SOUT[234] SOUT[235] SOUT[236] SOUT[237] SOUT[238] SOUT[239] SOUT[240] SOUT_DUM240 DUMMY DUMMY BICTI_L BICTI_L SCLK1 SCLK1 SCLK2 SCLK2 SFTCLK SFTCLK SFTCLKB SFTCLKB FLM FLM DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY X -5373.0 -5427.0 -5481.0 -5535.0 -5589.0 -5643.0 -5697.0 -5751.0 -5805.0 -5859.0 -5913.0 -5967.0 -6021.0 -6075.0 -6129.0 -6183.0 -6237.0 -6291.0 -6345.0 -6399.0 -6453.0 -6507.0 -6561.0 -6615.0 -6669.0 -6723.0 -6777.0 -6831.0 -6885.0 -6939.0 -6993.0 -7047.0 -7101.0 -7155.0 -7209.0 -7263.0 -7317.0 -7371.0 -7425.0 -7697.5 -7697.5 -7697.5 -7697.5 -7697.5 -7697.5 -7697.5 -7697.5 -7697.5 -7697.5 -7697.5 Y 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 572.5 298.0 244.0 190.0 136.0 82.0 28.0 -26.0 -80.0 -134.0 -188.0 -242.0 NO 551 NAME DUMMY X -7697.5 Y -296.0
14
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary PIN DESCRIPTION
POWER SUPPLY PINS
Table6: Power supply pin description Symbol I/O Description Power supply for internal logic and internal RAM. Internally, voltage regulator output is connected to this pin. Connect a capacitor for stabilization. Don't apply any external power to this pin. Internal power for RAM. Connect this pin to VDD externally. Regulated logic power voltage (1.5V) I/O power supply. (1.65V ~ 3.3V) Power supply for analog circuits. (VCI : 2.5 ~ 3.3V) An internal reference power supply for VCI1 amp. Analog power supply (VCI_MDDI : 2.5 ~ 3.3V) System ground (0V). System ground level for I/O A reference level for the grayscale voltage generation circuit. Connect this pin to an external resistor when a source driver is used to adjust grayscale levels for each panel. A reference voltage for 1st booster. A reference voltage input pin for power block when using an external VCIR generation mode. Input pin for applying VLOUT1 voltage level / 1st booster output pin. Recommend to connect VLIN1 to VLOUT1. Input pin for applying VLOUT2 voltage level / 2nd booster output pin. Recommend to connect VLIN2 to VLOUT2. Input pin for applying VLOUT3 voltage level / 3rd booster output pin. Recommend to connect VLIN3 to VLOUT3. External capacitor connection pins used for the 1'st booster circuit. External capacitor connection pins used for the 2nd booster circuit.
VDD
Power
MVDD RVDD VDD3 VCI VCI_MDDI VSS VSSA VSSC VSS_MDDI VGS VCI1 VCIRIN VLIN1 / VLOUT1 VLIN2 / VLOUT2 VLIN3 / VLOUT3 C11P,C11M C12P,C12M C21P,C21M
Power Power Power Power Power Ground Power I I/O I
I/O
I/O
I/O
I/O I/O
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table7: Power supply pin description(Continued) Symbol C31P,C31M C32P,C32M VREG1OUT VGH VGL VINT VSP ELVDD MTPG MTPD Vex I/O I/O I/O O O O O I I I I Description External capacitor connection pins used for the 3rd booster circuit. A reference level for the grayscale voltage with the amplitude between VLOUT1 and GND. The positive voltage used in the gate driver. The negative voltage used in the gate driver. A voltage for initializing an OLED panel. Power supply for the external photo sensor. If not use, this pin must be open. Power supply for the generation of VSP. If not use, this pin must be fixed to VSS level. A voltage for the MTP programming (Initialization, Erasing, and Programming). If not use, this pin must be open. A voltage for the MTP programming (Initialization, Erasing, and Programming). If not use, this pin must be open. Must be fixed to VSS level.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SYSTEM / RGB INTERFACE PINS
Symbol S_PB MDDI_EN ID_MIB I/O I I I Table8: System interface pin description Description Selects the CPU interface mode "Low" = Parallel Interface, "High" = Serial Interface Selects the MDDI interface "Low" = MDDI Disable, "High" = MDDI Enable Selects the CPU type "Low" = Intel 80x-system, "High" = Motorola 68x-system If S-PB = "High", the pin is used as ID setting bit for a device code. Chip select signal input pin. Low: S6E63D6 is selected and can be accessed High: S6E63D6 is not selected and cannot be accessed Register select pin. Low: Index/status, High: Instruction parameter, GRAM data Must be fixed at VDD3 level when not used.
Pin function CPU type 68-system 80-system Serial Peripheral Interface (SPI) CPU type 68-system 80-system RW Pin description Read/Write operation selection pin. Low: Write, High: Read Write strobe signal. (Input pin) Data is fetched at the rising edge. The synchronous clock signal. (Input pin) Pin description Read/Write operation enable pin. Read strobe signal. (Input pin) Read out data at the low level.
CSB
I
RS
I
RW_WRB/ SCL
I
WRB SCL Pin function E
E_RDB
I
RDB
When SPI mode is selected, fix this pin at VDD3 level. SDI SDO RESETB I O I For a serial peripheral interface (SPI), input data is fetched at the rising edge of the SCL signal. Fix SDI pin at VSS level if the pin is not used. For a serial peripheral interface (SPI), serves as the serial data output pin (SDO). Successive bits are output at the falling edge of the SCL signal. Reset pin Initializes the IC when low. Should be reset after power-on. Bi-directional data bus. When CPU I/F, 18-bit interface : DB 17-0 16-bit interface : DB 17-10, DB 8-1 9-bit interface : DB 8-0 8-bit interface : DB 8-1 When RGB I/F, 18-bit interface : DB 17-0 16-bit interface : DB 17-10, DB 8-1 6-bit interface : DB 8-3 Fix unused pin to the VSS level.
DB17-DB0
I/O
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Symbol I/O Table9: System interface pin description (Continued) Description Data enable signal pin for RGB interface. EPL="0": Only in case of ENABLE="Low", the IC can be access via RGB interface. EPL="1": Only in case of ENABLE="High", the IC can be access via RGB interface ENABLE I EPL ENABLE GRAM write 0 0 Valid 0 1 Invalid 1 0 Invalid 1 1 Valid Fix ENABLE pin at VSS level if the pin is not used. Frame-synchronizing signal. VSPL= "0": Low active, VSPL="1": High active Fix this pin at VSS level if the pin is not used. Line-synchronizing signal. HSPL="0": Low active, HSPL="1": High active Fix this pin at VSS level if the pin is not used. Input pin for clock signal of external interface: dot clock. DPL="0": Display data is fetched at DOTCLK's rising edge DPL="1": Display data is fetched at DOTCLK's falling edge Fix this pin at VSS level if the pin is not used. GRAM address Updated Held Held Updated
VSYNC
I
HSYNC
I
DOTCLK
I
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Tabel10: MDDI pin description Symbol MDP MDN MSP MSN GPIO[9:0] (DB[17:8]) S_CSB (DB[7]) I/O I/O I/O I I I/O Description Positive MDDI data input/output. If MDDI is not used, this pad should be floating. Negative MDDI data input/output. If MDDI is not used, this pad should be floating. Positive MDDI strobe input. If MDDI is not used, this pad should be floating. Negative MDDI strobe input. If MDDI is not used, this pad should be floating. General purpose input/output If GPIO is not used in MDDI mode, this pin should be fixed at VSS level. Chip select for Sub Panel Driver IC Low: Sub Panel Driver IC is selected and can be accessed. High: Sub Panel Driver IC is not selected and can not be accessed. If sub panel is not used in MDDI mode, this pin should be floating Register select for Sub Panel Driver IC Low : Index/status, High : Control Must be fixed at VSS level, when this signal is not used. If sub panel is not used in MDDI mode, this pin should be floating Write Strobe signal for Sub Panel Driver IC Only 80-system 18/16 bit mode is enabled, so Data is fetched at the rising edge. If sub panel is not used in MDDI mode, this pin should be floating For Sub Panel, this pin can be used to transfer DB[8:0] data to Sub Panel Driver IC. If sub panel is not used in MDDI mode, this pin should be floating.
O
S_RS (DB[6]) S_WRB (DB[5]) S_DB[8-0] (DB[4:0], TE, TEST_OUT[2:0]) HSYNC VSYNC ENABLE DOTCLK RW_WRB E_RDB RS CSB
O
O
O
I
In MDDI mode, Fixed at VSS level.
I I
In MDDI mode, Fixed at VDD3 level. In MDDI mode, Fixed at VDD3 level.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DISPLAY PINS
Symbol SOUT[1:240] FLM SFTCLK, SFTCLKB SCLK1, SCLK2 CLA, CLB, CLC BICTL_L BICTL_R EX_FLM EX_CLK, EX_CLKB ESR EL_ON I/O O O O O O O O O O O O Table11: Display pin description Description Source driver output pins. The direction of them is determined by the value of SS register. Start pulse of vertical line shift. Clock for gate driver shift. LTPS signals LTPS signals LTPS signal LTPS signal Don't use this pin. IC maker's test pins. Don't use this pin. IC maker's test pins. Shift register enable signal The external ELVDD regulator enable pin
MISCELLANEOUS PINS
Table12: Oscillator and internal power regulator pin description Symbol DUMMYR[3:1] DUMMYL[3:1] DUMMY V0/V63 VDD3DUM VSSDUM FUSE_EN RTEST EN_EXCLK EXCLK TEST_MODE[1:0] TEST_IN[6:0] TE TEST_OUT[2:0] I/O O O O I I I I I I O O Description Contact resistance measurement pin. In normal operation, leave this pin open Dummy pins don't care. Leave these pins open. Gamma voltage monitoring pin. This pin is connected to VDD3 line internally. Use for to connect neighbor-setting pins. This pin is connected to VSS line internally. Use for to connect neighbor-setting pins. Don't use this pin. IC maker's test pins. This pin must be tied to VDD3. Don't use this pin. IC maker's test pins. This pin must be tied to VSS. Don't use this pin. IC maker's test pins. Fix this pin at VSS level if the pin is not used. Don't use this pin. IC maker's test pins. Fix this pin at VSS level if the pin is not used. Don't use this pin. IC maker's test pins. Fix this pin at VSS level if the pin is not used. Don't use this pin. IC maker's test pins. Fix this pin at VSS level if the pin is not used. Tearing effect output pin. In normal operation, leave this pin open. Output pins used only for test purpose at vendor-side. In normal operation, leave this pin open.
20
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary FUNCTIONAL DESCRIPTION
SYSTEM INTERFACE
The S6E63D6 has ten high-speed system interfaces: an 80-system 18-/16-/9-/8-bit bus, a 68-system 18-/16-/9-/8-bit and two type serial interface (SPI: Serial Peripheral Interface). The S6E63D6 has three 18-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information for control register and GRAM. The WDR temporarily stores data to be written into control register and GRAM. The RDR temporarily stores data read from GRAM. Data written into the GRAM from CPU is initially written to the WDR and then written to the GRAM automatically. Data is read through the RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are valid. Execution time for instruction, except oscillation start, is 0-clock cycle so that instructions can be written in succession. Table13: Register Selection (18-/16-/9-/8- Parallel Interface) E_RDB RS Operations 1 0 Write index to IR 1 0 Read internal status 1 1 Write to control register and GRAM through WDR 1 1 Read from GRAM through RDR 1 0 Write index to IR 0 0 Read internal status 1 1 Write to control register and GRAM through WDR 0 1 Read from GRAM through RDR
SYSTEM 68
80
RW_WRB 0 1 0 1 0 1 0 1
CSB 0 1
Table14: CSB signal (GRAM update control) Operation Data is written to GRAM, GRAM address is updated Data is not written to GRAM, GRAM address is not updated Table15: Register Selection (Serial Peripheral Interface) RS bit Operation 0 Write index to IR 0 Read internal status 1 Write data to control register and GRAM through WDR 1 Read data from GRAM through RDR
R/W bit 0 1 0 1
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
HIGH SPEED SERIAL INTERFACE (MDDI)
This interface will be introduced, see the section "Description of MDDI Interface"
SUB PANEL CONTROL
Sub panel control block will be introduced, see the section "Description of Sub Panel Control"
EXTERNAL INTERFACE (RGB-I/F)
The S6E63D6 incorporates RGB interface as external interface for motion picture display. When the RGB interface is selected, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for display. The RGB data for display (DB17-0) are written according to enable signal (ENABLE) in synchronization with VSYNC, HSYNC, and DOTCLK signal. This allows flicker-free updating of the screen. See the section on the EXTERNAL DISPLAY INTERFACE.
ADDRESS COUNTER (AC)
The address counter (AC) assigns address to GRAM. When an address-set-instruction is written to the IR, the address information is sent from IR to AC. After writing to the GRAM, the address value of AC is automatically increased/ decreased by 1 according to ID1-0 bit of control register. After reading data from GRAM, the AC is updated automatically.
GRAPHICS RAM (GRAM)
The graphics RAM (GRAM) has 18-bits/pixel and stores the bit-pattern data for 240-RGB x 320-dot display.
TIMING GENERATOR
The Panel Interface Controller generates timing signals for LTPS drive. Also it generates control signals for the operation of internal circuits such as source driver and GRAM. The GRAM read operations done by this Timing Generator and GRAM write operations done through system interface are performed independently to avoid the interference between them.
GRAYSCALE VOLTAGE GENERATOR
The grayscale voltage circuit generates OLED driving voltage that corresponds to the grayscale levels as specified in the grayscale gamma-adjusting registers. 262,144 possible colors can be displayed at the same time by this LSI. Gamma is set for R,G, and B individually.
OSCILLATION CIRCUIT (OSC)
The S6E63D6 can provide R-C oscillation simply through the internal oscillation-resistor. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the internal register. Since R-C oscillation stops during the standby mode, current consumption can be reduced. For details, see the OSCILLATION CIRCUIT section.
22
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SOURCE DRIVER CIRCUIT
The source driving circuit of S6E63D6 consists of a 240 source drivers (SOUT[1] to SOUT[240]). Image data is latched when 240-pixel data has arrived. The latched data then enables the source drivers to generate drive waveform outputs. The SS register can change the shift direction of 240 source driver output data for the device-mount configuration.
LTPS PANEL INTERFACE CIRCUIT
LTPS panel interface circuit does level-shift operation and outputs to control LTPS panel.
23
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GRAM ADDRESS MAP
The image data stored in GRAM corresponds to pixel data on display as shown below:
Figure4: GRAM address (SS="0")
Figure5: GRAM address (SS="1" )
24
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary INSTRUCTIONS
The S6E63D6 uses the 18-bit bus architecture. Before the internal operation of the S6E63D6 starts, control information is stored temporarily in the registers described below to allow high-speed interfacing with a high-performance microcomputer. The internal operation of the S6E63D6 is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB17 to DB0), make up the S6E63D6 instructions. There are seven categories of instructions that: Specify the index Control the display Control power management Set internal GRAM addresses Transfer data to and from the internal GRAM Set grayscale level for the internal grayscale palette table Interface with the LTPS driver and power supply IC
Normally, instructions that write data are used the most. However, an auto-update of internal GRAM addresses after each data write can lighten the microcomputer program load. As instructions are executed in 0 cycles, they can be written in succession. The 16-bit instruction assignment differs from interface-setup (18-/16-/9-/8-/SPI), so instructions should be fetched according to the data format shown below:
68/80-system 18-bit Interface
INPUT DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
68/80-system 16-bit Interface/SPI(Serial Peripheral Interface)
INPUT DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
68/80-system 9-bit Interface
1st Transmission 2nd Transmission DB 2 DB 1 DB 0 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
INPUT DATA
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
68/80-system 8-bit Interface
1st Transmission DB 17 8 DB 16 7 DB 15 6 DB 14 5 DB 13 4 DB 12 3 DB 11 2 DB 10 1 DB DB 17 8 DB DB 16 7 DB DB 15 6 2nd Transmission DB DB 14 5 DB DB 13 4 DB DB 12 3 DB DB 11 2 DB DB 10 1
INPUT DATA
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
INSTRUCTION TABLE
Table16: Instruction Table
Reg. Index No IR I/F Control W 0 Set index register value R/W RS IB 15 X IB 14 X IB 13 X IB 12 X IB 11 X IB 10 X IB 9 X IB 8 X IB 7 ID7 IB 6 ID6 IB 5 ID5 IB 4 ID4 IB 3 ID3 IB 2 ID2 IB 1 ID1 IB 0 ID0
SR
R W
0 0
Status Read No Operation
X
X
X
X
X
X
X
L8
L7
L6
L5
L4
L3
L2
L1
L0
R0h
No operation
R01h
W
1
Display Duty control
FP3
FP2
FP1
FP0
BP3
BP2
BP1
BP0
X
X
NL5
NL4
NL3
NL2
NL1
NL0
R02h
W
1
RGB Interface Control
X
X
X
X
X
X
X
RM
DM
X
RIM1
RIM0
VSPL
HSPL
EPL
DPL
R03h
W
1
Entry Mode
CLS
MDT1
MDT0
BGR
X
X
X
SS
X
X
I/D1
I/D0
X
X
X
AM
R04h
W
1
Clock Control
X
X
X
X
X
X
X
X
X
X
DCR1
DCR0
X
X
X
X DISP_O N REV
Display Control
R05h
W
1
Display Control1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R06h
W
1
Display Control2
X
X
X
X
X
X
X
X
X
X
X
CL
X
X
TEMON
R07h
W W
1 1
Panel IF Control1
X
X
X
CLWEA CLWEA CLWEA CLWEA CLWEA 4 3 2 1 0 CLWEB CLWEB CLWEB CLWEB CLWEB 4 3 2 1 0
X
X
X
X
X
X
X
X
R08h
Panel IF Control2 Panel IF Control3
X
X
X
X
X
X
CLWEC CLWEC CLWEC CLWEC CLWeC 4 3 2 1 0 SHE0 X CLTE2 CLTE1 CLTE0
R09h
W
1
SCTE3 SCTE2 SCTE1 SCTE0 SCWE3 SCWE2 SCWE1 SCWE0
X
SHE2
SHE1
R0Ah Device Read
W
1
Panel IF Control4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GTCON GTCON 1 0 1 1
R0Fh
R
0
Device code read
1
1
0
0
0
0
1
1
1
1
0
1
0
0
R10h
W
1
Stand By
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STB
R12h
W
1
Power Gen1
X
X
X
X
X
X
X
X
X
X
X
X
VC3
VC2
VC1
VC0
Power Control
R13h
W
1
Power Gen2
X
X
VINT3
VINT2
VINT1
VINT0
X
VGH3
VGH2
VGH1
VGH0
X
VGL3
VGL2
VGL1
VGL0
R14h
W
1
Power Step Up Control1
X
DC22
DC21
DC0
DC12
DC11
DC10
X
X
X
X
X
X
BT1
BT0
R18h
W
1
Oscillator Control
X
X
X
X
X
X
X
X
X
X
RADJ5 RADJ4 RADJ3 RADJ2 RADJ1 RADJ0 GAMM SDUM_ A_TES ON T AD5 AD4
R1Ah
W
1
Source Driver Control
X
X
X
X
X
X
X
X
X
X
X
SAP2
SAP1
SAP0
R20h
W
1
X GRAM address set AD16-0: Set GRAM X
X
X
X
X
X
X
X
AD7
AD6
AD3
AD2
AD1
AD0
GRAM Access
R21h
W W
1 1 1 GRAM Write GRAM Read
X
X
X
X
X
X
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
WD17-0 : Pin assignment varies according to the interface method
R22h R RD17-0 : Pin assignment varies according to the interface method
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table17: Instruction Table(Continued)
Reg. Index No R23h I/F Control R24h W 0 X Vertical Scroll Control R31h W 1 X X X X X X X SEA8 SEA7 SEA6 SEA5 SEA4 SEA3 SEA2 SEA1 SEA0 X X X X X W 0 I/F Select Select 9/8-Bit Data Bus Interface X SSA8 SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 R/W RS IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0
Select 18/16-Bit Data Bus Interface
R30h
W
1
R32h
W
1
Vertical Scroll Control 2
X
X
X
X
X
X
X
SST8
SST7
SST6
SST5
SST4
SST3
SST2
SST1
SST0
Position Control
R33h
W
1
X Partial Screen Driving Position X
X
X
X
X
X
X
SS18
SS17
SS16
SS15
SS14
SS13
SS12
SS11
SS10
R34h
W
1
X
X
X
X
X
X
SE18
SE17
SE16
SE15
SE14
SE13
SE12
SE11
SE10
R35h
W
1
X Vertical RAM Address Position X
X
X
X
X
X
X
VSA8
VSA7
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
R36h
W
1
X
X
X
X
X
X
VEA8
VEA7
VEA6
VEA5
VEA4
VEA3
VEA2
VEA1
VEA0
R37h
W
1
Horizontal RAM Address Position Client initiated wake-up MDDI Link wake-up start position
HSA7
HSA6
HSA5
HSA4
HSA3
HSA2
HSA1
HSA0
HEA7
HEA6
HEA5
HEA4
HEA3
HEA2
HEA1
HEA0 VWAKE _EN X
38h
W
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
39h MDDI I/F
W
1
WKL8
WKL7
WKL6
WKL5
WKL4
WKL3
WKL2
WKL1
WKL0
X
WKF3
WKF2
WKF1
WKF0
X
3Ah
W
1
X
X X
X
X
X
X
X
X
SUB_S SUB_S SUB_S SUB_S SUB_S SUB_S SUB_S SUB_S EL7 EL 6 EL 5 EL 4 EL 3 EL 2 EL 1 EL 0 SUB_W SUB_W SUB_W SUB_W SUB_W SUB_W SUB_W SUB_W R7 R6 R5 R4 R3 R2 R1 R0 FCV_E N X X X MPU_M STN_E ODE N SUB_I M1 SUB_I M0
3Bh
W
1
Sub panel control
X
X
X
X
X
X
X
3C
W
1
X
X
X
X
X
X
X
X
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table19: Instruction Table(Continued)
Reg. Index No R60h W 1 R/W RS IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0
Test Key
X
X
X
X
X
X
X
X MTP_W RB X
0
0
0
0 MTP_S EL
1
1
1
1
R61h
W
1
MTP Selection
X
X R21_D K2
X R21_D K1
X
X
X
X
X R63_D K3
X R63_D K2
X R63_D K1
X
X
X
MTP_E RB
R62h MTP Control R63h
W
1
MTP Register Setting R
X
R21_D R21_BT R21_BT R21_BT K0 2 1 0 G21_B T2 G21_B T1 G21_B T0
R63_D R63_BT R63_BT R63_BT R63_BT K0 3 2 1 0 G63_B T3 G63_B T2 G63_B T1 G63_B T0
W
1
MTP Register Setting G
X
G21_D G21_D G21_D K2 K1 K0 B21_D K2 X B21_D K1 X
X
G63_D G63_D G63_D G63_D K3 K2 K1 K0 B63_D K3 X B63_D K2 X B63_D K1 X
R64h
W
1
MTP Register Setting B
X
B21_D B21_BT B21_BT B21_BT K0 2 1 0 X X X X
X
B63_D B63_BT B63_BT B63_BT B63_BT K0 3 2 1 0 X X E_OST E_OST E_OST 2 1 _0 GPIO2 GPIO_ CON2 GPIO1 GPIO_ CON1 GPIO0 GPIO_ CON0
R65h
W
1
MTP Register Offset
X
X
R66h
W
1
GPIO value
X
X
X
X
X
X
GPIO9 GPIO_ CON9
GPIO8 GPIO_ CON8
GPIO7 GPIO_ CON7
GPIO6 GPIO_ CON6
GPIO5 GPIO_ CON5
GPIO4 GPIO_ CON4
GPIO3 GPIO_ CON3
R67h GPIO Control R68h
W
1
in/output control
X
X
X
X
X
X
W
1
GPIO Clear
X
X
X
X
X
X
GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR 9 8 7 6 5 4 3 2 1 0 GPIO_ EN9 GPIO_ EN8 GPIO_ EN7 GPIO_ EN6 GPIO_ EN5 GPIO_ EN4 GPIO_ EN3 GPIO_ EN2 GPIO_ EN1 GPIO_ EN0
R69h
W
1
GPIO interrupt enable
X
X
X
X
X
X
R6Ah
W
1
GPIO polarity selection Gamma Top Bottom Control R Gamma Top Bottom Control G Gamma Top Bottom Control B Gamma Control R 1,2
X
X
X
X
X
X
GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL 9 8 7 6 5 4 3 2 1 0 CR52 CR51 CR50 X X X CR03 CR02 CR01 CR00
R70h
W
1
X
X
CR56
CR55
CR54
CR53
R71h
W
1
X
X
CG56
CG55
CG54
CG53
CG52
CG51
CG50
X
X
X
CG03
CG02
CG01
CG00
R72h
W
1
X
X
CB56
CB55
CB54
CB53
CB52
CB51
CB50
X
X
X
CB03
CB02
CB01
CB00
R73h
W
1
X
X
CR15
CR14
CR13
CR12
CR11
CR10
X
X
CR25
CR24
CR23
CR22
CR21
CR20
Gamma Control
R74h
W
1
Gamma Control R 3,4
X
X
CR35
CR34
CR33
CR32
CR31
CR30
X
X
CR45
CR44
CR43
CR42
CR41
CR40
R75h
W
1
Gamma Control G 1,2
X
X
CG15
CG14
CG13
CG12
CG11
CG10
X
X
CG25
CG24
CG23
CG22
CG21
CG20
R76h
W
1
Gamma Control G 3,4
X
X
CG35
CG34
CG33
CG32
CG31
CG30
X
X
CG45
CG44
CG43
CG44
CG41
CG40
R77h
W
1
Gamma Control B 1,2
X
X
CB15
CB14
CB13
CB12
CB11
CB10
X
X
CB25
CB24
CB23
CB22
CB21
CB20
R78h
W
1
Gamma Control B 3,4
X
X
CB35
CB34
CB33
CB32
CB31
CB30
X
X
CB45
CB44
CB43
CB42
CB41
CB40
R80h
W
1
Gamma Select
X
X
X
X
X
X
X
X
X
X
X
X
GS_SE GS_SE GS_SE GS_SE L3 L2 L1 L0
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary Instruction Descriptions
Index The index instruction specifies indexes. It sets the register number in the range of 0000000b to 1111111b in binary form. However, do not access index registers and instruction bits that are not allocated in this document.
R/W W RS 0 IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
X
IB6 ID6
IB5 ID5
IB4 ID4
IB3 ID3
IB2 ID2
IB1 ID1
IB0 ID0
Status Read The status read instruction reads out the internal status of the IC.
R/W R RS 0 IB15 0 IB14 0 IB13 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 L8 IB7 L7 IB6 L6 IB5 L5 IB4 L4 IB3 L3 IB2 L2 IB1 L1 IB0 L0
L8-0: Indicate the position of horizontal line currently being driven.
No Operation (R00h)
R/W W RS 0 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
No Operation
This command does not have any effect on the display module. However it can be used to terminate Memory Write and Read in 22h command.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DISPLAY DUTY CONTROL (R01h)
R/W W RS 1 IB15 FP3 IB14 FP2 IB13 FP1 IB12 FP0 IB11 BP3 IB10 BP2 IB9 BP1 IB8 BP0 IB7 X IB6 X IB5 NL5 IB4 NL4 IB3 NL3 IB2 NL2 IB1 NL1 IB0 NL0
*01h Initial Value = 1000_1000_XX10_1000 FP / BP Sets the period of Blank Area, which is placed at the beginning and the end of a frame. FP[3:0] is for a Front Porch and BP[3:0] is for a Back Porch. When Front Porch and Back Porch are set, the settings should meet the following conditions. BP+FP TBD lines FP TBD lines BP TBD lines When S6E63D6 operates in External Clock Operation mode, the Back Porch (BP) will start on the falling edge of the VSYNC signal and display operation begins just after the Back Porch period. The Front Porch (FP) will start when data of the number of lines specified by the NL has been displayed. During the period between the completion of the Front Porch and the next VSYNC signal, the display will remain blank. Table20: Blank Period Control with FP and BP FP[3:0] (BP[3:0]) Number of Raster Periods In Front (Back) Porch 0000 0001 0010 0011 0100 --1000 --1100 1101 1110 1111 SETTING DISABLE SETTING DISABLE 2 3 4 --8 --12 13 14 SETTING DISABLE
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
NL Specifies the number of lines driving OLED drive. The number of lines for the OLED drive can be adjusted for every eight lines. The selected value should be equal to or larger than the size of the panel to be driven. GRAM address mapping is not affected by the value of the drive duty ratio. Table21: NL and Drive Duty Display Size Drive Line ~ 240 X 160 240 X168 240X176 240X184 --240 X 312 240 X 320 ~ SETTING DISABLE SETTING DISABLE 160 168 176 184 --312 320
NL[5:0] 00_0000 01_0011 01_0100 01_0101 01_0110 01_0111 --10_0111 10_1000 10_1001 11_1111
[NOTE] A back porch period and a front porch period will be inserted as a blank period before and after driving all LTPS lines.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
RGB INTERFACE CONTROL (R02h)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 RM IB7 DM IB6 X IB5 RIM 1 IB4 RIM 0 IB3 VSP L IB2 HSP L IB1 EPL IB0 DPL
*02h Initial Value = XXXX_XXX0_0X00_0000 RM Specifies the interface for GRAM accesse as shown below. This register and DM register can be set independently. DM Specifies the display operation mode. The interface can be set based on the bit of DM. In Internal Clock Opeartion mode the source clock for display operation comes from internal oscillator while in External Clock Opeartion mode it comes from RGB interface(DOTCLK, VSYNC, HSYNC). Table22: RM, DM, GRAM Access Interface and Display Operation Mode DM GRAM Access Interface Display operation mode 0 1 System interface RGB interface Internal clock operation External clock operation
RM 0 1
[NOTE] [RM, DM]= 01, [RM, DM]=10 setting disable.
RIM Specifies RGB interface mode when the RGB interface is used. This register is valid when RM is set to "1". DM and this register should be set before proper display operation is performed through the RGB interface. Table23: RIM and RGB Interface Mode RGB Interface mode 18-bit RGB interface (one transfer per pixel) 16-bit RGB interface (one transfer per pixel) 6-bit RGB interface (three transfers per pixel) SETTING DISABLE
RIM[1:0] 00 01 10 11
33
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
You should notice that some display functions, which will be described later, cannot be used according to the display mode shown below. Table24: Display Functions and Display Modes Function External Clock Operation Internal Clock Operation Mode Mode Partial Display Scroll Function Rotation Mirroring Window Function Cannot be used Cannot be used Cannot be used Cannot be used Cannot be used Can be used Can be used Can be used Can be used Can be used
Depending on the external display interface setting, various interfaces can be specified to match the display state. While displaying motion pictures (RGB interface), the data for display can be written in high-speed write mode, which achieves both low power consumption and high-speed access. Table25: Display State and Interface Display State Still Pictures Motion Pictures
[NOTE]
Operation Mode Internal Clock RGB interface
RAM Access (RM) System interface (RM=0) RGB interface (RM=1)
Display Operation Mode (DM) Internal clock (DM=0) RGB interface (DM=1)
1) The instruction register can only be set through the system interface(SPI). 2) The RGB interface mode should not be set during operation. For the transition flow for each operation mode, see the External Display Interface section.
Internal Clock Mode All display operation is controlled by signals generated by the internal clock in internal clock mode. All inputs through the external display interface are invalid. The internal RAM can be accessed only via the system interface. RGB Interface Mode The display operations are controlled by the frame synchronization clock (VSYNC), raster-row synchronization signal (HSYNC), and dot clock (DOTCLK) in RGB interface mode. These signals should be supplied during display operation in this mode. The display data is transferred to the internal RAM via DB17-0 for each pixel. Combining the function of the high-speed write mode and the window address enables display of both the motion picture area and the internal RAM area simultaneously. In this method, data is only transferred when the screen is updated, which reduces the amount of data transferred. The periods of the front (FP), back (BP) porch, and the display are automatically generated in the S6E63D6 by counting the raster-row synchronization signal (HSYNC) based on the frame synchronization signal (VSYNC).
34
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
VSPL Determines the active polarity of VSYNC. Table26: VSPL and VSYNC VSYNC 0 (1) 1 (0)
VSPL 0 (1) 0 (1) HSPL
Description Valid (Valid) Invalid (Invalid)
Determines the active polarity of HSYNC. Table27: HSPL and VSYNC HSYNC 0 (1) 1 (0)
HSPL 0 (1) 0 (1) EPL
Description Valid (Valid) Invalid (Invalid)
Determines the active polarity of ENABLE for using RGB interface. Table28: EPL, ENABLE and RAM access ENABLE RAM Write 0 (1) 1 (0) Valid (Valid) Invalid (Invalid)
EPL 0 (1) 0 (1) DPL
RAM Address Updated (Updated) Hold (Hold)
Determines the active polarity of DOTCLK. Table29: HSPL and VSYNC DOTCLK () ()
DPL 0 (1) 0 (1)
Description Valid (Valid) Invalid (Invalid)
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
ENTRY MODE (R03h)
R/W W RS 1 IB15 CLS IB14 MDT 1 IB13 MDT 0 IB12 BGR IB11
X
IB10
X
IB9
X
IB8 SS
IB7
X
IB6
X
IB5 I/D1
IB4 I/D0
IB3
X
IB2
X
IB1
X
IB0 AM
*03h Initial Value = 0000_XXX0_XX11_XXX0 CLS: This bit is used to define the color and interface bus format, When MDT0-1 = 00 CLS = 0 : 65K-color mode through 8-bit(Index address 24h) or 16-bit bus(Index address 23h) CLS = 1 : 262K-color mode through 9-bit(Index address 24h) or 18-bit bus(Index address 23h) MDT1: This bit is active on the 80-system of 8-bit bus, and the data for 1-pixel is transported to the memory for 3 write cycles. This bit is on the 80-system of 16-bit bus, and the data for 1-pixel is transported to the memory for 2 write cycles. When the 80-system interface mode is not set in the 8-bit or16-bit mode, set MDT1 bit to be "0". MDT0: When 8-bit or16-bit 80 interface mode and MDT1 bit =1, MDT0 defines color depth for the IC. 8-bit (80-system), MDT0 = 0: 262k-color mode (3 times of 6-bit data transfer to GRAM) 8-bit (80-system), MDT0 = 1: 65k-color mode (5-bit, 6-bit, 5-bit data transfer to GRAM) 16-bit (80-system), MDT0 = 0: 262k-color mode (16-bit, 2-bit data transfer to GRAM) 16-bit (80-system), MDT0 = 1: 262k-color mode (2-bit, 16-bit data transfer to GRAM) Interface Mode * MDT1 0 MDT0 0 Write data to GRAM Default value. Multiple Data Transfer(MDT1-0) function is not available. Data Transfer is controlled by interface mode. (Depends on S_PB, ID_MIB pins, CLS register and Index address 23h or 24h) Multiple Data Transfer(MDT1-0) function is not available.
1st Transmission DB 8 DB 7 DB 6 DB 5 DB 4 2nd Transmission DB DB DB DB DB 3 17 16 15 14 8 7 6 5 3rd Transmission DB 12 3
80/68 system 8-bit
0 1
1 0
INPUT DATA
DB DB DB DB DB DB DB 13 12 17 16 15 14 13 4 3 8 7 6 5 4
RGB Arrangement Output
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S(n)
Note: n= 1 to 240
1
INPUT DATA
DB 8 17
1st Transmission DB 7 16 DB 6 15 DB 5 14 DB 4 13 DB 3 12 DB 8 17
2nd Transmission DB 7 16 DB 6 15 DB 5 14 DB 4 13 DB 3 12 DB 8 17
3rd Transmission DB 7 16 DB 6 15 DB 5 14 DB 4 13 DB 3 12
RGB Arrangement Output
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S(n)
Note: n= 1 to 240
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Interface Mode 80/68 system 16-bit MDT1 0 MDT0 1 Data Assignment
1
0
INPUT DATA
DB 17 DB 16 DB 15 DB 14 DB 13 DB 12
1st Transmission DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3
2nd Transmission
DB 2
DB 1
DB 17
DB 16
RGB Arrangement Output
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S(n)
Note: n= 1 to 240
1
1st Transmission DB 2 DB 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12
2nd Transmission DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
INPUT DATA
RGB Arrangement Output
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S(n)
Note: n= 1 to 240
37
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
BGR: About writing 18-bit data to GRAM, it is changed into . - BGR = 0 ; {DB[17:12], DB[11:6], DB[5:0]} is assigned to {R, G, B}. Actually the analog value that corresponds to DB[17:12] is output firstly at source output - BGR = 1 ; {DB[17:12], DB[11:6], DB[5:0]} is assigned to {B, G, R}. Actually the analog value that corresponds to DB[5:0] is output firstly at source output. SS Selects the direction of the source driver channel in pixel unit. When user changes the value of SS, memory should be updated to apply the change. Table30: Source Output Direction Control with SS (SS = "1") S240 S239 S238 S3 S2 G1 G2 G3 G4 G5 G6 G7 G8 M G313 G314 G315 G316 G317 G318 G319 G320
"00000"H "00100"H "00200"H "00300"H "00400"H "00500"H "00600"H "00700"H M "13800"H "13900"H "13A00"H "13B00"H "13C00"H "13D00"H "13E00"H "13F00"H "00001"H "00101"H "00201"H "00301"H "00401"H "00501"H "00601"H "00701"H M "13801"H "13901"H "13A01"H "13B01"H "13C01"H "13D01"H "13E01"H "13F01"H "00002"H "00102"H "00202"H "00302"H "00402"H "00502"H "00602"H "00702"H M "13802"H "13902"H "13A02"H "13B02"H "13C02"H "13D02"H "13E02"H "13F02"H ********** ********** ********** ********** ********** ********** ********** ********** M ********* ********* ********* ********* ********* ********* ********* ********* "000ED"H "001ED"H "002ED"H "003ED"H "004ED"H "005ED"H "006ED"H "007ED"H M "138ED"H "139ED"H "13AED"H "13BED"H "13CED"H "13DED"H "13EED"H "13FED"H "000EE"H "001EE"H "002EE"H "003EE"H "004EE"H "005EE"H "006EE"H "007EE"H M "138EE"H "139EE"H "13AEE"H "13BEE"H "13CEE"H "13DEE"H "13EEE"H "13FEE"H
S1
"000EF"H "001EF"H "002EF"H "003EF"H "004EF"H "005EF"H "006EF"H "007EF"H M "138EF"H "139EF"H "13AEF"H "13BEF"H "13CEF"H "13DEF"H "13EEF"H "13FEF"H
[NOTE] For the case of SS = "0", refer to "GRAM ADDRESS MAP" presented earlier. You should notice that the order of source output is reversed.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
ID When ID[1], ID[0] = 1, the address counter (AC) is automatically increased by 1 after the data is written to the GRAM. When ID[1], ID[0] = 0, the AC is automatically decreased by 1 after the data is written to the GRAM. The increment/decrement setting of the address counter using ID[1:0] is done independently for the horizontal address and vertical address. AM Sets the automatic update method of the AC after the data is written to GRAM. When AM = "0", the data is continuously written in horizontally. When AM = "1", the data is continuously written vertically. When window addresses are specified, the GRAM in the window range can be written to according to the ID[1:0] and AM. Table31: Address Direction Setting ID[1:0] = "00" ID[1:0] = "01" ID[1:0] = "10" H: decrement H: increment H: decrement V: decrement V: decrement V: increment
00000h 00000h 00000h
ID[1:0] = "11" H: increment V: increment
00000h
AM="0" Horizontal Update
13FEFh 13FEFh 13FEFh 13FEFh
0000h
0000h
0000h
0000h
AM="1" Vertical Update
13FEFh
13FEFh
13FEFh
13FEFh
[NOTE] When window addresses have been set, the GRAM can only be written within the window.
When AM or ID is set, the start address should be written accordingly prior to memory write.
39
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
CLOCK CONTROL (R04h)
R/W W RS 1 IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
X
IB6
X
IB5 DCR 1
IB4 DCR 0
IB3
X
IB2
X
IB1
X
IB0
X
*04h Initial Value = XXXX_XXXX_XX00_XXXX
DCR Sets the division ratio of step -up clock, DCCLK, in External Clock Operation mode. In this case, DOTCLK must be input periodically and continuously. Table32: DCR and Division Ratio of DCCLK Division ratio of DCCLK DOTCLK / 4 DOTCLK / 8 DOTCLK / 16 DOTCLK / 32
DCR[1:0] 00 01 10 11
40
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DISPLAY CONTROL - 1 (R05h)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 X IB6 X IB5 X IB4 x IB3 X IB2 X IB1 X IB0 DISP_ ON
*05h Initial Value = XXXX_XXXX_XXXX_XXX0
DISP_ON Output from the Frame Memory is enabled. This register makes No Change of contents of frame memory DISP_ON = 0 (Display is black image),
(Example) Memory Display
DISP_ON = 1,
(Example) Memory Display
For more information, see the Instruction Set Up Sequence.
41
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DISPLAY CONTROL - 2 (R06h)
R/W W RS 1 IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
X
IB6
X
IB5
X
IB4 CL
IB3
X
IB2
X
IB1 TEM ON
IB0 REV
*06h Initial Value = XXXX_XXXX_XXX0_XX00 CL Sets color depth of display. Table33: Color Control by CL
CL
0 1
[NOTE] It depend on interface mode(18bit or 16bit).
Description
262,144 / 65,536 colors [NOTE] 8 colors
TEMON : TEMON = 0, Disable the TE output signal from the FLM signal line for preventing Tearing Effect. TEMON = 1, Enable the TE output signal from the FLM signal line for preventing Tearing Effect.
REV Displays all characters and graphics display sections with reversal when REV = 1. The grayscale level can be reversed. Table34: REV and Source Output Level in Normal Display Area REV 0 GRAM Data 6'b000000 ~ 6'b111111 6'b000000 ~ 6'b111111 Source Output Level in Displayed Area V0 (High Voltage) ~ V63(Low Voltage) V63 (Low Voltage) ~ V0 (High Voltage)
1
42
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PANEL INTERFACE CONTROL - 1 (R07h) PANEL INTERFACE CONTROL - 2 (R08h)
R/W W RS 1 IB15
X
IB14
X
IB13
X
IB12
IB11
IB10 CLW EA2
IB9 CLW EA1
IB8 CLW EA0
IB7
X
IB6
X
IB5
X
IB4
X
IB3
X
IB2
X
IB1
X
IB0
X
CLWE CLW A4 EA3
*07h Initial Value = XXX0_1100_XXXX_XXXX
R/W W RS 1 IB15
X
IB14
X
IB13
X
IB12
IB11
IB10 CLW EB2
IB9 CLW EB1
IB8 CLW EB0
IB7
X
IB6
X
IB5
X
IB4 CLW EC4
IB3 CLW EC3
IB2 CLW EC2
IB1 CLW EC1
IB0 CLW EC0
CLWE CLW B4 EB3
*08h Initial Value = XXX0_1100_XXX0_1100 CLWEA, CLWEB, CLWEC Specifies the interval time of CLA, CLB, CLC respectively. Table35: CLWEx and the intervals CLWEx[4:0] 0_0000 0_0001 0_0010 --0_1100 --1_1110 1_1111 Description SETTING DISABLE 0.5 HCLK 1 HCLK --6 HCLK --15 HCLK 15.5 HCLK
[NOTE] For the information of HCLK, refer to "FRAME FREQUENCY CACULATION"
43
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PANEL INTERFACE CONTROL - 3 (R09h)
R/W W RS 1 IB15 SCT E3 IB14 SCT E2 IB13 IB12 IB11 IB10 SC WE2 IB9 SC WE1 IB8 SC WE0 IB7
X
IB6 SHE 2
IB5 SHE 1
IB4 SHE 0
IB3
X
IB2 CLT E2
IB1 CLT E1
IB0 CLT E0
SCT SC SCTE0 E1 WE3
*09h Initial Value = 1000_0101_X001_X010 SCTE Specifies the rising position of SCLK1, SCLK2 Table36: SCTE and the rising position of SCLK1, SCLK2 SCTE[3:0] Description 0000 0001 0010 --1000 --1110 1111 SCWE Specifies the width of SCLK1, SCLK2 Table37: SCWE and the width of SCLK1, SCLK2 Description 8 HCLKs 8.5 HCLKs 9 HCLKs --10.5 HCLKs --15 HCLKs 15.5 HCLKs 16.5 HCLKs 17 HCLKs 17.5 HCLKs ---20.5 HCLKs ---23.5 HCLKs 24 HCLKs
SCWE[3:0] 0000 0001 0010 --0101 --1110 1111
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SHE Specifies the latency of CLB and CLC. Table38: SHE and the latency of CLB and CLC Description SETTING DISABLE 0.5 HCLK 1 HCLK --3 HCLK 3.5 HCLK
SHE[2:0] 000 001 010 --110 111 CLTE
Specifies the falling position of CLA. Table39: CLTE and the falling position of CLA Description SETTING DISABLE 0.5 HCLK 1 HCLK 1.5 HCLKs --3 HCLKs 3.5 HCLKs
CLTE[2:0] 000 001 010 011 --110 111
45
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PANEL INTERFACE CONTROL - 4 (R0Ah)
R/W W RS 1 IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
X
IB6
X
IB5
X
IB4
X
IB3
X
IB2
X
IB1 GTC ON1
IB0 GTC ON0
*0Ah Initial Value = XXXX_XXXX_XXXX_XX00 GTCON Specifies the panel interface signals. Table40: GTCON and the panel interface signals Output Signal GTCON[1:0]=00 BICTL_L BICTL_R FLM SFTCLK SFTCLKB SCLK1 SCLK2 EX_FLM EX_CLK EX_CLKB ESR CLA CLB CLC VGH VGH FLM SFTCLK SFTCLKB SCLK1 SCLK2 EX_FLM EX_CLK EX_CLKB ESR CLA CLB CLC GTCON[1:0]=01 VGL VGL FLM SFTCLK SFTCLKB SCLK2 SCLK1 EX_FLM EX_CLKB EX_CLK ESR CLA CLB CLC GTCON[1:0]=10 VGH VGH FLM VGL VGH SCLK1 SCLK2 EX_FLM VGL VGH ESR CLA CLB CLC GTCON[1:0]=11 VGL VGL FLM VGL VGH SCLK2 SCLK1 EX_FLM VGL VGH ESR CLA CLB CLC
Output Pin
46
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
STAND BY (R10h)
R/W W RS 1 IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
X
IB6
X
IB5
X
IB4
X
IB3
X
IB2
X
IB1
X
IB0 STB
*10h Initial Value = XXXX_XXXX_XXXX_XXX1 STB When STB = "1", S6E63D6 enters Standby mode, where display operation completely stops including the internal R-C oscillation. Furthermore, no external clock pulses are supplied. For details, see the "STANDBY SEQENCE" described later. Only the following instructions can be executed during the standby mode. - Standby mode cancel ; STB = "0"
47
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
POWER GEN1 (R12h)
R/W W RS 1 IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
X
IB6
X
IB5 X
IB4
X
IB3 VC3
IB2 VC2
IB1 VC1
IB0 VC0
*12h Initial Value = XXXX_XXXX_XXXX_1000 V reference voltage of VLOUT1, VLOUT2 and VLOUT3. VC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VCI1 [Without Load] 2.10 V 2.15 V 2.20 V 2.25 V 2.30 V 2.35 V 2.40 V 2.45 V 2.50 V 2.55 V 2.60 V 2.65 V 2.70 V 2.75 V Setting Disable Setting Disable
[NOTE] Set VCI1 in the range of VCI > VCI1 + 0.3V
48
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
POWER GEN2 (R13h)
R/W W RS 1 IB15 X IB14 X IB13 IB12 IB11 IB10 VINT3 VINT2 VINT1 VINT0 IB9 X IB8 IB7 IB6 IB5 VGH3 VGH2 VGH1 VGH0 IB4 X IB3 VGL3 IB2 VGL2 IB1 VGL1 IB0 VGL0
*13h Initial Value = XX01_01X0_011X_1010 VINT3[3:0] set VINT (control voltage of OLED Panel). It can be amplified -2.0 to -0.5 times of VCIR.
VINT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
[NOTE] Set VINIT in the range of V VINT > VLOUT3 + 1.0V
VINT value -1.0 V -1.2 V -1.4 V -1.6 V -1.8 V -2.0 V -2.2 V -2.4 V -2.6 V -2.8 V -3.0 V -3.2 V -3.4 V -3.6 V -3.8 V -4.0 V
VGH[3:0] set VGH (High Voltage Level for Gate).
VGH[3:0] 0000 0001 0010 0011 0100 0101 0110 0111
VGH value 4.6 V 4.8 V 5.0 V 5.2 V 5.4 V 5.6 V 5.8 V 6.0 V 49
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
1000 1001 1010 1011 1100 1101 1110 1111
[NOTE] Set VGH in the range of VGH < VLOUT2-1.0V
6.2 V 6.4 V 6.6 V Setting disable Setting disable Setting disable Setting disable Setting disable
VGL[3:0] bits set VGL (Low Voltage Level for Gate).
VGL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
[NOTE] Set VGL in the range of VGL > VLOUT3 + 1.0V
VGL Value -5.0 V -5.2 V -5.4 V -5.6 V -5.8 V -6.0 V -6.2 V -6.4 V -6.6 V -6.8 V -7.0 V -7.2 V -7.4 V -7.6 V -7.8 V Setting disable
50
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
POWER STEP UP CONTROL 1 (R14h)
R/W W RS 1 IB15 X IB14 DC2 2 IB13 DC2 1 IB12 DC2 0 IB11 X IB10 DC1 2 IB9 DC1 1 IB8 DC1 0 IB7 X IB6 X IB5 X IB4 X IB3 X IB2 X IB1 BT1 IB0 BT0
*14h Initial Value = X100_X010_XXXX_XX00 DC2[2:0] is the operating frequency in the step-up circuit 2 is selected. DC1[2:0] is the operating frequency in the step-up circuit 1 is selected. Step-up Cycle in Step-up Circuit 2 DM=0 000 001 010 011 100 101 110 OSC_CK/16 OSC_CK/24 OSC_CK/32 OSC_CK/48 OSC_CK/64 OSC_CK/96 OSC_CK/128 DM=1 DCCLK/16 DCCLK/24 DCCLK/32 DCCLK/48 DCCLK/64 DCCLK/96 DCCLK/128 000 001 010 011 100 101 110 Step-up Cycle in Step-up Circuit 1 DM=0 OSC_CK/16 OSC_CK/24 OSC_CK/32 OSC_CK/48 OSC_CK/64 OSC_CK/96 OSC_CK/128 DM=1 DCCLK/16 DCCLK/24 DCCLK/32 DCCLK/48 DCCLK/64 DCCLK/96 DCCLK/128 DCCLK/256
DC2[2:0]
DC1[2:0]
111 OSC_CK/256 DCCLK/256 111 OSC_CK/256 [NOTE] DM is Display Method. DCCLK is for External I/F. See instruction R02h, R04h.
BT[1:0] switch the output factor of step-up. Adjust scale factor of the step-up circuit by the voltage used. BT[1:0] 00 01 10 11 VLOUT1 VCI1 x 2 VCI1 x 2 VCI1 x 2 VCI1 x 2 VLOUT2 VCI1 x 4 VCI1 x 4 VCI1 x 3 VCI1 x 3 VLOUT3 -(VCI1 x 4) -(VCI1 x 3) -(VCI1 x 4) -(VCI1 x 3)
51
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
START OSCILLATION (R18h)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 X IB6 X IB5 IB4 IB3 IB2 IB1 IB0 RADJ5 RADJ4 RADJ3 RADJ2 RADJ1 RADJ0
*18h Initial Value = XXXX_XXXX_XX01_1111 Select the oscillation frequency of internal oscillator. RADJ[5:0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 Oscillation Speed x 0.543(Min.) x 0.551 x 0.560 x 0.568 x 0.578 x 0.586 x 0.596 x 0.606 x 0.615 x 0.626 x 0.637 x 0.647 x 0.660 x 0.671 x 0.685 x 0.697 x 0.707 x 0.721 x 0.736 x 0.751 x 0.766 RADJ[5:0] 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 ~ 111111 Oscillation Speed x 0.782 x 0.800 x 0.818 x 0.835 x 0.855 x 0.877 x 0.899 x 0.921 x 0.946 x 0.972 x 1.000 x 1.037 x 1.067 x 1.101 x 1.135 x 1.172 x 1.212 x 1.256 x 1.302 X1.352(Max.) Setting disable
52
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SOURCE DRIVER CONTROL (R1Ah)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 X IB6 X IB5 GAMMA _TEST IB4 SDUM _ON IB3 X IB2 SAP 2 IB1 SAP 1 IB0 SAP 0
*1Ah Initial Value = XXXX _XXXX_XX00_X101 When GAMMA_TEST='1', V0/V63 pins are shorted to each gamma voltage V0/V63 and gamma voltage V0/V63 can be monitored or be forced by external voltage level. GAMMA_TEST 0 1 V0 / V63 Hi-z V0 / V63
When SDUM_ON='1', SOUT_DUM1 and SOUT_DUM240 pins are shorted to SOUT[1], SOUT[240] output and can be monitored. SDUM_ON 0 1 SOUT_DUM1 / SOUT_DUM240 Hi-z SOUT[1] / SOUT[240]
Adjust the slew-rate of the operational amplifier of the source driver. If higher SAP[2:0] is set, OLED panel having higher resolution of higher frame frequency can be driven because the slew-rate of the operational amplifier is increased. But, these bits must be set as adequate value because the amount of fixed current of the operational amplifier is also adjusted. During non-display, when SAP[2:0]="000", operational amplifiers are turned off, so current consumption can be reduced SAP[2:0] 000 001 010 011 100 101 110 111 Slew-Rate of Operational Amplifier Slow Slow or medium Medium Medium or small fast Small fast Fast Big fast Amount of Current in Operational Amplifier Small Small or medium Medium Medium or small large Small large large Big large
Operation of the operational amplifier stops.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GRAM ADDRESS SET (R20h) GRAM ADDRESS SET (R21h)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 AD7 IB6 AD6 IB5 AD5 IB4 AD4 IB3 AD3 IB2 AD2 IB1 AD1 IB0 AD0
*20h Initial Value = XXXX _XXXX_0000_0000
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 AD1 6 IB7 AD1 5 IB6 AD1 4 IB5 AD1 3 IB4 AD1 2 IB3 AD1 1 IB2 AD1 0 IB1 AD9 IB0 AD8
*21h Initial Value = XXXX _XXX0_0000_0000
AD You can write initial GRAM address into internal Address Counter (AC). When GRAM data is transferred through System Interface or RGB Interface, the AC is automatically updated according to AM and ID. This allows consecutive write without re-setting address in AC. But when GRAM data is read, the AC is not automatically updated. GRAM address setting is not allowed in Standby mode. Ensure that the address is set within the specified window area. When RGB interface is used (RM="1") to access GRAM, AD[16:0] will be set in the address counter at the falling edge of the VSYNC signal. And when one uses System Interface to access GRAM (RM = "0"), AD[16:0] will be set upon the execution of an instruction. Table41: GRAM Address Range GRAM setting Bitmap data for G1 Bitmap data for G2 Bitmap data for G3 Bitmap data for G4 M M Bitmap data for G317 Bitmap data for G318 Bitmap data for G319 Bitmap data for G320
AD[16:0]
"00000h" to "00AFh" "00100h" to "01AFh" "00200h" to "02AFh" "00300h" to "03AFh" M M "13C00h" to "13CEFh" "13D00h" to "13DEFh" "13E00h" to "13EEFh" "13F00h" to "13FEFh"
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
WRITE DATA TO GRAM (R22h)
R/W W W RS 1 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
RAM write data (WD17-0): Pin assignment varies according to the interface method. (see the following figure for more information)
WD15
WD14
WD13
WD12
WD11
WD10
WD9
WD8
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
When RGB-interface
WD17-0: Input data for GRAM can be expanded to 18 bits. The expansion format varies according to the interface method. The input data selects the grayscale level. After a write, the address is automatically updated according to I/D bit settings. The GRAM cannot be accessed in standby mode. When 16- or 8-bit interface is in use, the write data is expanded to 18 bits by writing the MSB of the data to its LSB. When data is written to RAM used by RGB interface via the system interface, please make sure that write data conflicts do not occur. When the 18-bit RGB interface is in use, 18-bit data is written to RAM via DB17-0 and 262,144-colors are available. When the 16-bit RGB interface is in use, the MSB is written to its LSB and 65,536-colors are available.
Start
Window Address Set (index 35h, 36h, 37h)
Start Address Set (index 20h, 21h)
Index Write (22h)
Write Data Address is updated by 1 Yes
Write More ? No Write Index 00h or another where, Address hold
( Memory Write )
Figure6: Memory Data Write Sequence
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
READ DATA FROM GRAM (R22h)
R/ W R R S 1 DB1 7 DB1 6 DB1 5 DB1 4 DB1 3 DB1 2 DB1 1 DB1 0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RAM Read data (RD17-0): Pin assignment varies according to the interface method. (see the following figure for more information)
RD17-0: Read 18-bit data from the GRAM. When the data is read to the CPU, the first-word read immediately after the GRAM address setting is latched from the GRAM to the internal read-data latch. The data on the data bus (DB17-0) becomes invalid and the second-word read is normal. In case of 16-/8-bit interface, the LSB of color data will not be read. This function is not available in RGB interface mode.
Start Set Index 23h and RM = 0 Window Address Set (index 35h, 36h, 37h) Start Address Set (index 20h, 21h) Index Write (22h) Read Dummy Data Start Set Index 24h and RM = 0 Window Address Set (index 35h, 36h, 37h) Start Address Set (index 20h, 21h) Index Write (22h) Read Dummy Data 2 times
Read Valid Data Address is updated by 1 Yes
Read Upper Valid Data Read Lower Valid Data Address is updated by 1 Yes
Read More ? No Write Index 00h or another Where, Address hold
Read More ? No Write Index 00h or another Where, Address hold
18-/16- System Interface
9-/8- System Interface
Figure7: Memory Data Read Sequence
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
SELECT DATA BUS 1 (R23h)
R/W W RS 0 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
Select 18-/16-bit Data Bus Interface
SELECT DATA BUS 2 (R24h)
R/W W RS 0 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
Select 9-/8-bit Data Bus Interface
We can select system interface mode by pins and instruction as following.
Table42: System Interface mode
Pins MDDI _EN S_PB ID_MIB Index Address Registers Command ( CLS ) 0 (80 8bit) 1( 80 9bit) Index 23 h (18/16bit) 0 (Parallel 0 ) default & 24h (9/8bit) 1 (68 mode) Index 23 h (18/16bit) 1 (68 18bit) 1 (Serial) 1 x ID x x x x x 0 (68 16bit) 1 (68 9bit) 1( 80 18bit) 0 (68 8bit) 0 (80 16bit) Command MDT[1] 0 default & 24h (9/8bit) 0 (80 mode) 1 x 0 1 x 0 1 x 0 1 x x x Command MDT[0] x 0 1 X 0 1 X X X 0 1 X 0 1 x x x x Description 80-system 8-bit 65k bus interface 80-system 8-bit 260k bus interface 80-system 8-bit 65k bus interface 80-system 9-bit 260k bus interface 80-system 16-bit 65k bus interface 80-system 16-bit 260k bus interface 80-system 16-bit 260k bus interface 80-system 18-bit 260k bus interface 68-system 8-bit 65k bus interface 68-system 8-bit 260k bus interface 68-system 8-bit 65k bus interface 68-system 9-bit 260k bus interface 68-system 16-bit 65k bus interface 68-system 16-bit 260k bus interface 68-system 16-bit 260k bus interface 68-system 18-bit 260k bus interface Serial peripheral interface (SPI)
[NOTE] For details, see the ENTRY MODE (Instruction R03h).
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
VERTICAL SCROLL CONTROL 1 (R30h, R31h)
R/W W W RS 1 1 IB15 X X IB14 X X IB13 X X IB12 X X IB11 X X IB10 X X IB9 X X IB8 SSA 8 SEA 8 IB7 SSA 7 SEA 7 IB6 SSA 6 SEA 6 IB5 SSA 5 SEA 5 IB4 SSA 4 SEA 4 IB3 SSA 3 SEA 3 IB2 SSA 2 SEA 2 IB1 SSA 1 SEA 1 IB0 SSA 0 SEA 0
*30h Initial Value = XXXX_XXX0_0000_0000 *31h Initial Value = XXXX_XXX1_0011_1111 SSA8-0: Specify scroll start address at the scroll display for vertical smooth scrolling. SSA8 0 0 0 0 0 0 1 1 1 1 SSA7 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 SSA6 0 0 0 0 0 0 : 1 1 1 1 SSA5 0 0 0 0 0 0 : : 1 1 1 1 SSA4 0 0 0 0 0 0 : SSA3 0 0 0 0 0 0 : 1 1 1 1 : 1 1 1 1 0 0 1 1 0 1 0 1 SSA2 0 0 0 0 1 1 SSA1 0 0 1 1 0 0 SSA0 0 1 0 1 0 1 Scroll Start Address 0 raster-row 1 raster-row 2 raster-row 3 raster-row 4 raster-row 5 raster-row : 316 raster-row 317 raster-row 318 raster-row 319 raster-row
SEA8-0: Specify scroll end address at the scroll display for vertical smooth scrolling. SEA8 0 0 0 0 0 0 1 1 1 SEA7 0 0 0 0 0 0 : 0 0 0 0 0 0 SEA6 0 0 0 0 0 0 : 1 1 1 SEA5 0 0 0 0 0 0 : : 1 1 1 SEA4 0 0 0 0 0 0 : SEA3 0 0 0 0 0 0 : 1 1 1 : 1 1 1 0 0 1 1 0 1 0 1 SEA2 0 0 0 0 1 1 SEA1 0 0 1 1 0 0 SEA0 0 1 0 1 0 1 Scroll End Address 0 raster-row 1 raster-row 2 raster-row 3 raster-row 4 raster-row 5 raster-row : 316 raster-row 317 raster-row 318 raster-row 319 raster-row
1 0 0 1 1 1 1 [NOTE] Don't set any higher raster-row than 319 ("13F"H) Set SS18-10 SSA8-0, if set out of range, SSA8-0 = SS18-10. Set SE18-10 SEA8-0, if set out of range, SEA8-0 = SE18-10
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
VERTICAL SCROLL CONTROL 2 (R32h)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 SST 8 IB7 SST 7 IB6 SST 6 IB5 SST 5 IB4 SST 4 IB3 SST 3 IB2 SST 2 IB1 SST 1 IB0 SST 0
*32h Initial Value = XXXX_XXX0_0000_0000 SST8-0: Specify scroll start and step at the scroll display for vertical smooth scrolling. Any raster-row from the 1st to 320th can be scrolled for the number of the raster-row. After 319th raster-row is displayed, the display restarts from the first raster-row. When SST8-0 = 00000000, Vertical Scroll Function is disabled. SST8 0 0 0 0 0 0 1 1 1 1 SST7 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 SST6 0 0 0 0 0 0 : 1 1 1 1 SST5 0 0 0 0 0 0 : : 1 1 1 1 SST4 0 0 0 0 0 0 : SST3 0 0 0 0 0 0 : 1 1 1 1 : 1 1 1 1 0 0 1 1 0 1 0 1 SST2 0 0 0 0 1 1 SST1 0 0 1 1 0 0 SST0 0 1 0 1 0 1 Scroll Step Scroll Disabled 1 raster-row 2 raster-row 3 raster-row 4 raster-row 5 raster-row : 316 raster-row 317 raster-row 318 raster-row 319 raster-row
[NOTE] Don't set any higher raster-row than 319 ("13F"H) Set SS18-10 < SSA8-0 + SST8-0 SEA8-0 SE18-10, if set out of range, Scroll function is disabled
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
Figure8: Vertical Scroll Display
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Preliminary
PARTIAL SCREEN DRIVING POSITION (R33h, R34h)
R/W W W RS 1 1 IB15 X X IB14 X X IB13 X X IB12 X X IB11 X X IB10 X X IB9 X X IB8 SS18 SE18 IB7 SS17 SE17 IB6 SS16 SE16 IB5 SS15 SE15 IB4 SS14 SE14 IB3 SS13 SE13 IB2 SS12 SE12 IB1 SS11 SE11 IB0 SS10 SE10
*33h Initial Value = XXXX_XXX0_0000_0000 *34h Initial Value = XXXX_XXX1_0011_1111 SS18-10: Specify the drive starting position for the first screen in a line unit. The OLED driving starts from the `set value +1' gate driver. SE18-10: Specify the driving end position for the screen in a line unit. The OLED driving is performed to the `set value + 1' gate driver. For instance, when SS18-10 = 019h and SE18-10 = 029h are set, the OLED driving is performed from G26 to G42, and non-display driving is performed for G1 to G25, G43, and others. Ensure that SS18-10 SE18-10 13Fh. [NOTE] DO NOT set the partial setting when the operation is in the normal display condition. Set this register only when in the partial display condition. Ex) SS18-0=007h and SE18-0=010h are performed from G8 to G17. The S6E63D6 can select and drive partial screens at any position with the screen-driving position registers (R33h, R34h). Any partial screens required for display are selectively driven and reducing OLED-driving voltage and power consumption.
Non-display area
G26 G42
OCT 1st 08:00 AM
Partial screen 17 raster-row driving
Non-display area
* Driving raster-row: NL5-0 = 101000 (320 lines) * Partial screen setting: SS18-10 = 019H, SE18-10 = 029H
Figure9: Driving On Partial Screen
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Preliminary
RESTRICTION ON PARTIAL DISPLAY AREA SETTING The following restrictions must be satisfied when setting the start line (SS18 to 10) and end line (SE18 to 10) of the partial screen driving position register (R33h, R34h) for the S6E63D6. Note that incorrect display may occur if the restrictions are not satisfied. Table43: Restrictions on the partial Screen Driving Position Register Setting Register setting (SE18 to 10) - (SS18 to 10) = NL*8 Display operation Full screen display Normally displays (SS18 to 10) to (SE18 to 10) Partial display Normally displays (SS18 to 10) to (SE18 to 10) Black display for all other times (RAM data is not related at all) Setting disabled
(SE18 to 10) - (SS18 to 10) < NL*8
(SE18 to 10) - (SS18 to 10) > NL*8 [NOTE] 000h SS18 to 10 SE18 to 10 13Fh
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
VERTICAL RAM ADDRESS POSITION (R35h,R36h) HORIZONTAL RAM ADDRESS POSITION (R37h)
R/W W W W RS 1 1 1 IB15 X X HSA 7 IB14 X X HSA 6 IB13 X X HSA 5 IB12 X X HSA 4 IB11 X X HSA 3 IB10 X X HSA 2 IB9 X X HSA 1 IB8 VSA 8 VEA 8 HSA 0 IB7 VSA 7 VEA 7 HEA 7 IB6 VSA 6 VEA 6 HEA 6 IB5 VSA 5 VEA 5 HEA 5 IB4 VSA 4 VEA 4 HEA 4 IB3 VSA 3 VEA 3 HEA 3 IB2 VSA 2 VEA 2 HEA 2 IB1 VSA 1 VEA 1 HEA 1 IB0 VSA 0 VEA 0 HEA 0
*35h Initial Value = XXXX_XXX0_0000_0000 *36h Initial Value = XXXX_XXX1_0011_1111 *37h Initial Value = 0000_0000_1110_1111 VSA8-0/VEA8-0: Specify the vertical start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by VSA8-0 to the address specified by VEA8-0. Note that an address must be set before RAM is written. HSA7-0/HEA7-0: Specify the horizontal start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by HSA7-0 to the address specified by HEA 7-0. Note that an address must be set before RAM is written..
HSA 00000h
HEA 000EFh
VSA Window Address Range -0 HSA HEA EFh VSA VEA 13Fh -0
Window
VEA GRAM 13F00h 13FEFh
Figure10: Window Address Function
[NOTE] Ensure that the Window addresses are within the GRAM address space.
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Preliminary
CLIENT INITIATED WAKE-UP (R38h)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 X IB6 X IB5 X IB4 X IB3 X IB2 X IB1 X IB0 VWAK E_EN
*38h Initial Value = XXXX_XXXX_XXXX_XXX0 VWAKE_EN : When VWAKE_EN is 1, client initiated wake-up is enabled. But parameter data IB[15:1] must be "0000h", otherwise, client initiated wake-up is disabled.
MDDI LINK WAKE-UP START POSITION (R39h)
R/W W RS 1 IB15 WKL 8 IB14 WKL 7 IB13 WKL 6 IB12 WKL 5 IB11 WKL 4 IB10 WKL 3 IB9 WKL 2 IB8 WKL 1 IB7 WKL 0 IB6 X IB5 WKF 3 IB4 WKF 2 IB3 WKF 1 IB2 WKF 0 IB1 X IB0 X
*39h Initial Value = 0000_0000_0X00_00XX WKF3-0 : When client initiated wake-up is used at MDDI, the frame position that data is updated is set by the value of WKF 3-0. The range of WKF is from `0000' to `1111'. If WKF is `0000', data is updated at the first frame, and if "1111" data update starts after 16th frame. WKL8-0 : When client initiated wakeup is used at MDDI, data is updated at the line the value of WKL7-0 in the frame that is set by WKF3-0. The range of WKL is from `000h' to `1FFh'. If WKL is `000h', data is updated at the first line, and if WKL is `0FFh', data update starts at the 256th line. Setting of WFK and WKL is needed for client-initiated link wake-up. For example, WKF is "0010" and WKL is "0001", data is updated at second line of third frame.
SUB PANEL CONTROL 1 (R3Ah / R3Bh)
R/W W W RS 1 1 IB15 X X IB14 X X IB13 X X IB12 X X IB11 X X IB10 X X IB9 X X IB8 X X IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 SUB_SEL SUB_WR
*3Ah Initial Value = XXXX_XXXX_0111_1010 *3Bh Initial Value = XXXX_XXXX_0010_0010 SUB_SEL : SUB_SEL is the index of main/sub panel selection. Initial value of SUB_SEL is `7Ah'. In MDDI mode, If written register address is `7Ah' (initial state: SUB_SEL is `7Ah') and register data is `0001h', then main panel is selected, and if that is "0000h", then sub panel is selected. Using SUB_SEL register, Main / Sub panel selection index change is possible. SUB_WR : SUB_WR is the index of sub panel data write. Initial value of SUB_WR is `22h'. When MDDI host transfer GRAM data to sub panel driver IC via video stream packet, SUB_WR (initially 22h), index for GRAM access is automatically transferred before GRAM data transfer. When sub panel driver IC uses other address, 22h address have to be changed. Then user can change SUB_WR value from 22h to other value.
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
SUB PANEL CONTROL 2 (R3Ch)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 FCV_ EN IB6 X IB5 X IB4 X IB3 MPU_ MODE IB2 STN _EN IB1 SUB _IM1 IB0 SUB _IM0
*3Ch Initial Value = XXXX_XXXX_0XXX_0000 SUB_IM1-0: set the sub-panel interface SUB_ SUB_ IM1 IM0 0 0 1 1 0 1 0 1 Interface 18bit 9bit 16bit 8bit
STN_EN: set the panel property. STN_EN = "1": STN panel. STN_EN = "0": TFT panel. MPU_MODE: set the MPU interfaces MPU_MODE = "1": 68 mode MPU_MODE = "0": 80 mode FCV_EN : data format conversion enable signal FCV_EN = "1": 16 bit data format conversion (not used) FCV_EN = "0": current 16bit data format
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Preliminary
TEST KEY COMMAND (R60h) MTP CONTROL (R61h) MTP REGISTER SETTING (R62h, R63h, R64h, R65h)
R/W W W W W W W RS 1 1 1 1 1 1 IB15 X X
X X X X
IB14 X X
IB13 X X
IB12 X X
IB11 X X
IB10 X X
IB9 X X
IB8 X MTP_ WRB
X X X X
IB7 0 X
IB6 0 X
IB5 0 X
IB4 0 MTP_ SEL
IB3 1 X
IB2 1 X
IB1 1 X
IB0 1 MTP_ ERB
R21_DK2 R21_DK1 R21_DK0 R21_BT2 R21_BT1 R21_BT0 G21_DK2 G21_DK1 G21_DK0 G21_BT2 G21_BT1 G21_BT0 B21_DK2 B21_DK1 B21_DK0 B21_BT2 B21_BT1 B21_BT0 X X X X X X
R63_DK3 R63_DK2 R63_DK1 R63_DK0 R63_BT3 R63_BT2 R63_BT1 R63_BT0 G63_DK3 G63_DK2 G63_DK1 G63_DK0 G63_BT3 G63_BT2 G63_BT1 G63_BT0 B63_DK3 B63_DK2 B63_DK1 B63_DK0 B63_BT3 B63_BT2 B63_BT1 B63_BT0 X X X X X E_OST2 E_OST1 E_OST_0
*Initial Value MTP_WRB: 1'b1, MTP_SEL: 1'b1, MTP_ERB: 1'b1 R21_DK[2:0]: 3'd0, R21_BT[2:0]: 3'd0, R63_DK[3:0]: 4'd0, R63_BT[3:0]: 4'd0 G21_DK[2:0]: 3'd0, G21_BT[2:0]: 3'd0, G63_DK[3:0]: 4'd0, G63_BT[3:0]: 4'd0 B21_DK[2:0]: 3'd0, B21_BT[2:0]: 3'd0, B63_DK[3:0]: 4'd0, B63_BT[3:0]: 4'd0 E_OST[2:0]:3'd0 Test Key Command : Protection command. When Test Key Command =8Ch, MTP_WRB and MTP_ERB are valid MTP_WRB: MTP Write enable signal. If you want to write data to MTP cell, set MTP_WRB = 0 MTP_SEL: Selects MTP value or register value added to CR5[6:0], CG5[6:0], CB5[6:0], CR3[5:0], CG3[5:0], and CB3[5:0] MTP_ERB: Enable for MTP initial or erase. When MTP_ERB = 0, MTP initialization or erase is enabled. R21_DK[3:0], R21_BT[[3:0]: V21(Red) offset compensation value. G21_DK[3:0], G21_BT[[3:0]: V21(Green) offset compensation value. B21_DK[3:0], B21_BT[[3:0]: V21(Blue) offset compensation value. R63_DK[4:0], R63_BT[[4:0]: V63(Red) offset compensation value. G63_DK[4:0], G63_BT[[4:0]: V63(Green) offset compensation value. B63_DK[4:0], B63_BT[[4:0]: V63(Blue) offset compensation value. E_OST[2:0]: ELVDD offset compensation value
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Preliminary
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Preliminary
R(G,B)_21[2:0] 011 010 001 000 111 110 101 100 complement offset value +3 +2 +1 0 -1 -2 -3 -4 R(G,B)_63[3:0] 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 complement offset value +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 E_OST[2:0] 011 010 001 000 111 110 101 100 complement offset value +3 +2 +1 0 -1 -2 -3 -4
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Start
RESET
Start
Enter Standby Mode ( STB = "1" ) Supply MTPG, MTPD ( MTPG = 21.5V), MTPD = 0V) Set Test Key ( TEST_KEY parameter = "0Fh" ) Enable Initialization ( MTP_ERB = "0" )
Display On after a RESET
Find Desired MTP value with MTP_SEL = "0"
Bad
Good
Initialization & Erase Flow
Wait 1ms or more
Enable MTP Write ( MTP_WRB = "0" )
Enter Standby Mode ( STB = "1" ) Supply MTPG, MTPD ( MTPG = 0V), MTPD = 16.5V) Set Test Key ( TEST_KEY Parameter = "0Fh" )
Wait 100ms or more
Disable MTP Write ( MTP_WRB = "1" ) Cut Off MTPG, MTPD ( MTPG = MTPD = floating )
Set Desired MTP Value
Initialization & Erase Flow
RESET
End End
A. Flow of MTP Initialization & Erase
B. Flow of MTP Program
Figure16: MTP Initialization, Erase and program
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
Figure17: Timing of MTP Program
Figure18: Timing of MTP Load
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GPIO CONTROL (R66h/R67h/R68h/R69h/R6Ah)
R/W W W W W W RS 1 1 1 1 1 IB15 X X X X X IB14 X X X X X IB13 X X X X X IB12 X X X X X IB11 X X X X X IB10 X X X X X IB9 GPI O9 GPI O_C ON9 GPC LR9 GPI O_E N9 GPP OL9 IB8 GPI O8 GPI O_C ON8 GPC LR8 GPI O_E N8 GPP OL8 IB7 GPI O7 GPI O_C ON7 GPC LR7 GPI O_E N7 GPP OL7 IB6 GPI O6 GPI O_C ON6 GPC LR6 GPI O_E N6 GPP OL6 IB5 GPI O5 GPI O_C ON5 GPC LR5 GPI O_E N5 GPP OL5 IB4 GPI O4 GPI O_C ON4 GPC LR4 GPI O_E N4 GPP OL4 IB3 GPI O3 GPI O_C ON3 GPC LR3 GPI O_E N3 GPP OL3 IB2 GPI O2 GPI O_C ON2 GPC LR2 GPI O_E N2 GPP OL2 IB1 GPI O1 GPI O_C ON1 GPC LR1 GPI O_E N1 GPP OL1 IB0 GPI O0 GPI O_C ON0 GPC LR0 GPI O_E N0 GPP OL0
*66h Initial Value = XXXX_XX00_0000_0000 *67h Initial Value = XXXX_XX00_0000_0000 *68h Initial Value = XXXX_XX00_0000_0000 *69h Initial Value = XXXX_XX00_0000_0000 *6Ah Initial Value = XXXX_XX11_1111_1111 GPIO: GPIO value. When GPIO is input mode, GPIO value is set to the register. GPIO_CON: Control of GPIO, When GPIO_CON is "0", then GPIO is input mode, and when "1", then GPIO is output mode GPCLR: After client is wakeup, GPIO GPIO_EN: When GPIO is set input, if GPIO_EN is "1", it acts as enable internal interrupt. GPPOL: If the bit is set to "1", GPIO interrupt happens at rising edge of GPIN, If set to "0", it happens at falling edge. For more information about these registers, refer to GPIO CONTROL section
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Preliminary
GAMMA CONTROL (R70h to R78h)
R/W W W W W W W W W W RS 1 1 1 1 1 1 1 1 1 IB15 X X X X X X X X X IB14 X X X X X X X X X IB13 CR56 CG56 CB56 CR15 CR35 CG15 CG35 CB15 CB35 IB12 CR55 CG55 CB55 CR14 CR34 CG14 CG34 CB14 CB34 IB11 CR54 CG54 CB54 CR13 CR33 CG13 CG33 CB13 CB33 IB10 CR53 CG53 CB53 CR12 CR32 CG12 CG32 CB12 CB32 IB9 CR52 IB8 CR51 IB7 CR50 IB6 X X X X X X X X X IB5 X X X CR25 CR45 IB4 X X X CR24 CR44 IB3 CR03 IB2 CR02 IB1 CR01 IB0 CR00
CG52 CG51 CG50 CB52 CR11 CR31 CB51 CR10 CR30 CB50 X X X X X X
CG03 CG02 CG01 CG00 CB03 CR23 CR43 CB02 CR22 CR42 CB01 CR21 CR41 CB00 CR20 CR40
CG11 CG10 CG31 CG30 CB11 CB31 CB10 CB30
CG25 CG24 CG23 CG22 CG21 CG20 CG45 CG44 CG43 CG44 CG41 CG40 CB25 CB45 CB24 CB44 CB23 CB43 CB22 CB42 CB21 CB41 CB20 CB40
These registers set the one of the 9 gamma sets according to GS_SEL[3:0] CR5[6:0]: The amplitude adjust register CR4[4:0]: The amplitude adjust register CR3[4:0]: The amplitude adjust register CR2[4:0]: The amplitude adjust register CR1[4:0]: The amplitude adjust register CR0[3:0]: The amplitude adjust register CG5[6:0]: The amplitude adjust register CG4[4:0]: The amplitude adjust register CG3[4:0]: The amplitude adjust register CG2[4:0]: The amplitude adjust register CG1[4:0]: The amplitude adjust register CG0[3:0]: The amplitude adjust register CB5[6:0]: The amplitude adjust register CB4[4:0]: The amplitude adjust register CB3[4:0]: The amplitude adjust register CB2[4:0]: The amplitude adjust register CB1[4:0]: The amplitude adjust register CB0[3:0]: The amplitude adjust register For details, see the GAMMA ADJUSTMENT FUNCTION.
GAMMA SELECT (R80h)
R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 X IB6 X IB5 X IB4 X IB3 GS_ SEL3 IB2 GS_ SEL2 IB1 GS_ SEL1 IB0 GS_ SEL0
*80h Initial Value = XXXX_XXXX_XXXX_0100 Selects the gamma set controlled by 70H ~ 78H
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Preliminary RESET FUNCTION
The S6E63D6 is initialized internally by RESET input. The reset input should be held `L' for at least 10us. Do not access the GRAM nor initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms).
INSTRUCTION SET INITIALIZATION
1. Display duty control (R01h) : FP3_0=1000, BP3_0=1000, NL5_0=10_1000 2. RGB interface control (R02h) : RM=0, DM=0, RIM1_0=00, VSPL=0, HSPL=0, EPL=0, DPL=0 3. Entry mode (R03h) : CLS=0, MDT1_0=00, BGR=0, SS=0, ID1_0=11, AM=0 4. Clock control (R04h) : DCR1_0=00 5. Display control 1 (R05h) : DISP_ON=0 6. Display control 2 (R06h) : CL=0, TEMON=0, REV=0 7. Panel interface control 1 (R07h) : CLWEA4_0=0_1100 8. Panel interface control 2 (R08h) : CLWEB4_0=0_1100, CLWEC4_0=0_1100 9. Panel interface control 3 (R09h) : SCTE3_0=1000, SCWE3_0=0101, SHE2_0=001, CLTE2_0=010 10. Panel interface control 4 (R0Ah) : GTCON1_0=00 11. Stand by (R10h) : STB=1 12. Power gen 1 (R12h) : VC3_0=1000 13. Power gen 2 (R13h) : VINT3_0=0101, VGH3_0=0011, VGL3_0=1010 14. Power step up control 1 (R14h) : DC22_0=100, DC12_0=010, BT1_0=00 15. Start oscillation (R18h) : RADJ5_0=01_1111 16. Source driver control (R1Ah) : GAMMA_TEST=0, SDUM_ON=0, SAP2_0=101 17. GRAM address set (R20h) : AD7_0=0000_0000 18. GRAM address set (R21h) : AD16_8=0_0000_0000 19. Vertical scroll control 1 (R30h, R31h) : SSA8_0=0_0000_0000, SEA8_0=1_0011_1111 20. Vertical scroll control 2 (R32h) : SST8_0=0_0000_0000 21. Partial screen driving position (R33h, R34h) : SS18_0=0_0000_0000, SE18_0=1_0011_1111 22. Vertical RAM address position (R35h, R36h) : VSA8_0=0_0000_0000, VEA8_0=1_0011_1111 23. Horizontal RAM address position (R37h) : HAS7_0=0000_0000, HEA7_0=1110_1111 24. Client initiated wake up (R38h) : VWAKE_EN=0 25. MDDI link wake up start position (R39h) : WKL8_0=0_0000_0000, WKF3_0=0000 26. Sub panel control 1(R3Ah, R3Bh) : SUB_SEL7_0=0111_1010, SUB_WR7_0=0010_0010 27. Sub panel control 2 (R3Ch) : FCV_EN=0, MPU_MODE=0, STN_EN=0, SUB_IM1_0=00 28. MTP control (R61h) : MTP_WRB=1, MTP_SEL=1, MTP_ERB=1 29. MTP register setting 1 (R62h) : R21_DK2_0=000, R21_BT2_0=000, R63_DK3_0=0000, R63_BT3_0=0000 30. MTP register setting 2 (R63h) : G21_DK2_0=000, G21_BT2_0=000, G63_DK3_0=0000, G63_BT3_0=0000 31. MTP register setting 3 (R64h) : B21_DK2_0=000, B21_BT2_0=000, B63_DK3_0=0000, B63_BT3_0=0000 32. MTP register setting 4 (R65h) : E_OST2_0=000 33. GPIO control (R66h, R67h, R68h. R69h, R6Ah) : GPIO9_0=00_0000_0000, GPIO_CON9_0=00_0000_0000 GPCLR9_0=00_0000_0000, GPIO_EN9_0=00_0000_0000, GPPOL9_0=11_1111_1111
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary POWER SUPPLY
PATTERN DIAGRAMS FOR VOLTAGE SETTING
The following figure shows a pattern diagram for the voltage setting and an example of waveforms.
Figure19: Pattern Diagram for Voltage Setting
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
VOLTAGE REGULATION FUNCTION
The S6E63D6 has the internal voltage regulator. By the use of this function, unexpected damages on internal logic circuit can be avoided. Furthermore, power consumption can also be obtained. Detailed function description and application configuration is described in the following diagram.
Figure20: Voltage Regulation Function
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary INTERFACE SPECIFICATION
The S6E63D6 incorporates a system interface, which is used to set instructions, and an external display interface, which is used to display motion pictures. Selecting these interfaces to match the screen data (motion picture or still picture) enables efficient transfer of data for display. The external display interface includes RGB interface. This allows flicker-free screen update. When RGB interface is selected, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for use in operating the display. The display data (DB17-0) is written according to the values of the data enable signal (ENABLE) in synchronization with the VSYNC, HSYNC, and DOTCLK signals. In addition, using the window address function enables rewriting only to the internal RAM area to display motion pictures. Using this function also enables simultaneously display of the motion picture area and the RAM data that was written.
HOSTs
S6E63D3
S_PB ID_MIB CSB RS RW_WRB E_RDB DB 18/16/9/8 Serial Peripheral Interface (CSB) RW_WRB/SCL SDI SDO VSYNC HSYNC ENABLE DOTCLK (DB) 18/16/6
CPU Interface
System Interface
RGB Interface
RGB Interface
Figure21: System Interface and RGB Interface
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Preliminary
SYSTEM INTERFACE
S6E63D6 is enabling to set instruction and access to RAM by selecting S_PB, ID_MIB pins and Instruction in the system interface mode. Table44: System Interface mode
Pins MDDI _EN S_PB ID_MIB Index Address Registers Command ( CLS ) 0 (80 8bit) 1( 80 9bit) Index 23 h (18/16bit) 0 (Parallel 0 ) default & 24h (9/8bit) 1 (68 mode) Index 23 h (18/16bit) 1 (68 18bit) 1 (Serial) 1 x ID x x x x x 0 (68 16bit) 1 (68 9bit) 1( 80 18bit) 0 (68 8bit) 0 (80 16bit) Command MDT[1] 0 default & 24h (9/8bit) 0 (80 mode) 1 x 0 1 x 0 1 x 0 1 x x x Command MDT[0] x 0 1 X 0 1 X X X 0 1 X 0 1 x x x x Description 80-system 8-bit 65k bus interface 80-system 8-bit 260k bus interface 80-system 8-bit 65k bus interface 80-system 9-bit 260k bus interface 80-system 16-bit 65k bus interface 80-system 16-bit 260k bus interface 80-system 16-bit 260k bus interface 80-system 18-bit 260k bus interface 68-system 8-bit 65k bus interface 68-system 8-bit 260k bus interface 68-system 8-bit 65k bus interface 68-system 9-bit 260k bus interface 68-system 16-bit 65k bus interface 68-system 16-bit 260k bus interface 68-system 16-bit 260k bus interface 68-system 18-bit 260k bus interface Serial peripheral interface (SPI)
[NOTE] For details, see the ENTRY MODE (Instruction R03h). We can select system interface mode by pins and instruction, don't care 8-/16-bit bus system after power on. 1. In case of 8/9-bit bus system.
Figure21: 8/9-bit bus system
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Preliminary
2. In case of 18/16-bit bus system
Figure22: 18/16-bit bus system
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Preliminary
68-SYSTEM 18-BIT BUS INTERFACE Bit Assignment
INPUT DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure23: Instruction Format For 18-Bit Interface
GRAM DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure24: RAM Data Write Format For 18-Bit Interface Timing Diagram There are 4 timing conditions for 68-system 18-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition.
Figure25: Timing Diagram of 68-System 18-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
68-SYSTEM 16-BIT BUS INTERFACE Bit Assignment
INPUT DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure26: Instruction Format For 16-Bit Interface
GRAM DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure27: RAM Data Write Format For 16-Bit Interface
Timing Diagram There are 4 timing conditions for 68-system 16-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition.
Figure28: Timing Diagram of 68-System 16-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
68-SYSTEM 9-BIT BUS INTERFACE Bit Assignment
1st Transmission
2nd Transmission DB 2 DB 1 DB 0 DB 17 8 DB 16 7 DB 15 5 DB 14 5 DB 13 4 DB 12 3 DB 11 2 DB 10 1 DB 9 0
INPUT DATA
DB 8
DB 7
DB 5
DB 5
DB 4
DB 3
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure29: Instruction Format For 9-Bit Interface
1st Transmission DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 DB 8 DB 7 DB 6
2nd Transmission DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
GRAM DATA
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure30: RAM Data Write Format For 9-Bit Interface Timing Diagram There are 4 timing conditions for 68-system 9-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the upper half word. Note that the upper byte must also be written when the index register is written.
Figure31: Timing Diagram of 68-System 9-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
68-SYSTEM 8-BIT BUS INTERFACE Bit Assignment
1st Transmission DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 17 8 DB 16 7 DB 15 6
2nd Transmission DB 14 5 DB 13 4 DB 12 3 DB 11 2 DB 10 1
INPUT DATA
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure32: Instruction Format For 8-Bit Interface
1st Transmission
2nd Transmission DB 2 DB 1 DB 17 8 DB 16 7 DB 15 6 DB 14 5 DB 13 4 DB 12 3 DB 11 2 DB 10 1
GRAM DATA
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure33: RAM Data Write Format For 8-Bit Interface Timing Diagram There are 4 timing conditions for 68-system 8-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the upper half word. Note that the upper byte must also be written when the index register is written.
Figure34: Timing Diagram of 68-System 8-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
80-SYSTEM 18-BIT BUS INTERFACE Bit Assignment
INPUT DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure35: Instruction Format For 18-Bit Interface
GRAM DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure36: RAM Data Write Format For 18-Bit Interface Timing Diagram There are 4 timing conditions for 80-system 18-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition.
Figure37: Timing Diagram of 80-System 18-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
80-SYSTEM 16-BIT BUS INTERFACE Bit Assignment
INPUT DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure38: Instruction Format For 16-Bit Interface
GRAM DATA
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure39: RAM Data Write Format For 16-Bit Interface
Timing Diagram There are 4 timing conditions for 80-system 16-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition.
Figure40: Timing Diagram of 80-System 16-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
80-SYSTEM 9-BIT BUS INTERFACE Bit Assignment
1st Transmission
2nd Transmission DB 2 DB 1 DB 0 DB 17 8 DB 16 7 DB 15 6 DB 14 5 DB 13 4 DB 12 3 DB 11 2 DB 10 1 DB 0 9
INPUT DATA
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure41: Instruction Format For 9-Bit Interface
1st Transmission DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 DB 8 DB 7 DB 6
2nd Transmission DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
GRAM DATA
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure42: RAM Data Write Format For 9-Bit Interface Timing Diagram There are 4 timing conditions for 80-system 9-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the upper half word. Note that the upper byte must also be written when the index register is written.
Figure43: Timing Diagram of 80-System 9-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
80-SYSTEM 8-BIT BUS INTERFACE Bit Assignment
1st Transmission DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 8 DB 7 DB 6
2nd Transmission DB 5 DB 4 DB 3 DB 2 DB 1
INPUT DATA
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure44: Instruction Format For 8-Bit Interface
1st Transmission
2nd Transmission DB 2 DB 1 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
GRAM DATA
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure45: RAM Data Write Format For 8-Bit Interface Timing Diagram There are 4 timing conditions for 80-system 8-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the upper half word. Note that the upper byte must also be written when the index register is written.
Figure46: Timing Diagram of 80-System 8-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
68-/80-SYSTEM 8-/9-BIT INTERFACE SYNCHRONIZATION FUNCTION The S6E63D6 supports the transfer synchronization function, which resets the upper/lower counter to count upper/lower 8-/9-bit data transfer in the 8-/9-bit bus interface. Noise causing transfer mismatch between the upper and lower bits can be corrected by a reset triggered by writing a "22h" instruction. The next transfer starts from the upper bits. Executing synchronization function periodically can recover any runaway in the display system.
Figure47: 8-/9-bit Interface Transfer Synchronization
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
SERIAL PERIPHERAL INTERFACE Setting the S_PB pin to the VDD3 level allows serial peripheral interface (SPI) transfer, using the chip select line (CS*), serial transfer clock line (SCL), serial input data (SDI), and serial output data (SDO). For a serial interface, the IM0/ID pin function uses an ID pin. If the chip is set up for serial interface, the DB17-0 pins are used only data bus of RGB Interface. The S6E63D6 initiates serial data transfer by transferring the start byte at the falling edge of CSB input. It ends serial data transfer at the rising edge of CSB input. The S6E63D6 is selected when the 6-bit chip address in the start byte matches the 6-bit device identification code that is assigned to the S6E63D6. When selected, the S6E63D6 receives the subsequent data string. The least significant bit (LSB) of the identification code can be determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be assigned to a single S6E63D6 because the seventh bit of the start byte is used as a register select bit (RS). That is, when RS = 0, data can be written to the index register or status can be read, and when RS = 1, an instruction can be issued or data can be written to or read from RAM. Read or write operation is selected according to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is 0, and is transmitted when the R/W bit is 1. After receiving the start byte, the S6E63D6 receives or transmits the subsequent data byte-by-byte. The data is transferred with the MSB first. All S6E63D6 instructions are 16 bits. Two bytes are received with the MSB first (DB17 to DB0), then the instructions are internally executed. After the start byte has been received, the first byte is fetched as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the instruction. Four bytes of RAM read data after the start byte are invalid. The S6E63D6 starts to read correct RAM data from the fifth byte. Table45: Start Byte Format 1 2 3 4 Device ID code 0 1 1 1 0 ID
Transfer bit Start byte format
S Transfer start
5
6
7 RS
8 R/W
NOTE: ID bit is selected by the ID_MIB pin.
RS 0 0 Bit Assignment
Table46: RS and R/W Bit Function R/W Function 0 Set index register 1 Read status
Figure48: Bit Assignment of Instructions on SPI
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
Timing Diagram
Figure49: Basic Timing Diagram of Register Data Transfer through SPI
Figure50: Timing Diagram of Consecutive Register Data-Write through SPI
Figure51: Timing Diagram of Register Read through SPI
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
INDEX AND PARAMETER RECOGNITION If more parameter command is being sent, exceed parameters are ignored.
Figure52: Index and parameter recognition with 8-/9-bit interface
Figure53: Index and parameter recognition with 18-/16-bit interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary EXTERNAL DISPLAY INTERFACE
The following interfaces are available as external display interface. It is determined by bit setting of RIM1-0. RAM accesses can be performed via the RGB interface. Table47: RIM Bits RGB Interface 18-bit RGB interface 16-bit RGB interface 6-bit RGB interface Setting disabled
RIM1 0 0 1 1 ENABLE SIGNAL
RIM0 0 1 0 1
DB Pin DB17 to 0 DB17 to10, 8 to 1 DB8 to3
The relationship between EPL and ENABLE signals is shown below. When ENABLE is not active, the address is not updates. When ENABLE is active, the address is updated. Table48: Relationship between EPL and ENABLE ENABLE RAM WRITE RAM ADDRESS 0 Valid Updated 1 Invalid Hold 0 Invalid Hold 1 Valid Update
EPL 0 0 1 1
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
18-Bit RGB interface Bit Assignment
Figure54: Bit Assignment of GRAM Data on 18bit RGB Interface 16-Bit RGB interface Bit Assignment
Figure55: Bit Assignment of GRAM Data on 16bit RGB Interface Timing Diagram
1 Frame VSYNC >= 1H Back Porch HSYNC DOTCLK ENABLE DB[17:0] A 1H Front Porch
B HSYNC DOTCLK ENABLE
>= 256CLK
1CLK
DB[17:0]
Figure56: Timing Diagram of 18/16bit RGB Interface
[NOTE]
1. 1 HSYNC Period must be >= 256 DOTCLK
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6-Bit RGB interface In order to transfer data on 6bit RGB Interface there should be three transfers. Bit Assignment
Figure57: Bit Assignment of GRAM Data on 6bit RGB Interface Timing Diagram
Figure58: Timing Diagram of 6bit RGB Interface
[NOTE] 1. Three clocks are regarded as one clock for transfer when data is transferred in 6-bit interface. VSYNC, HSYNC, ENABLE, DOTCLK, and DB[8:3] should be transferred in units of three clocks. 2. 1 HSYNC Period must be >= 256 * 3 DOTCLK
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Transfer Synchronization
Figure59: Transfer Synchronization Function in 6-bit RGB Interface mode
[NOTE] The figure shows Transfer Synchronization function for 6bit RGB Interface. S6E63D6 has a transfer counter to count 1st, 2nd and 3rd data transfer of 6bit RGB Interface. The transfer counter is reset on the falling edge of HSYNC and enters the 1st data transmission state. Transfer mismatch can be corrected at every new transfer restarts with HSYNC signal. In this method, when data is consecutively transferred in such a way as displaying motion pictures, the effect of transfer mismatch will be reduced and recovered by normal operation. [NOTE] The internal display is operated in units of three DOTCLKs. When DOTCLK is not input in units of pixels, clock mismatch occurs and the frame, which is operated, and the next frame are not displayed correctly.
Time chart for RGB interface is shown below. (In case of EPL = 0)
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INTERFACE SWAPPING FOR MEMORY ACCESS
DISPLAY MODES AND GRAM ACCESS CONTROL Display mode and RAM Access is controlled as shown below. For each display status, display mode control and RAM Access control are combined properly. Table49: DISPLAY MODE & RAM ACCESS CONTROL Display Status GRAM Access (RM) Display Mode (DM) Internal Clock Operation (Still Picture Display) RGB I/F (Displaying Motion Picture) MDDI interface (Displaying motion Pictures) System Interface (RM = 0) RGB Interface (RM = 1) System interface (RM=0) Internal Clock Operation (DM = 0) External Clock Operation (DM = 1) MDDI interface (D=0)
[NOTE 1] Only system interface can set Instruction register. [NOTE 2] When the RGB Interface is being operated do not change the RGB Interface mode (RIM).
Internal Clock Operation mode with System Interface
Every operation in Internal Clock Operation mode is done in synchronization with the internal clock which is generated by internal OSC. The signals input through RGB interface are all meaningless. Access to internal GRAM is done via system interface.
External Clock Operation mode with RGB Interface
In External Clock Operation mode, frame sync signal (VSYNC), line sync signal (HSYNC) and DOTCLK are used for display operation. Display data is transferred in the unit of pixel through DB bus and saved to GRAM.
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USAGE ON EXTERNAL DISPLAY INTERFACE
1. When external display interface is in use, the following functions are not available. Table50: External Display Interface and Internal Display Operation Function External Display Interface Internal Display Operation Partial Display Scroll Function Rotation Mirroring Window Function Not Available Not Available Not Available Not Available Not Available Available Available Available Available Available
2. VSYNC, HSYNC, and DOTCLK signals should be supplied during display operation via RGB interface. 3. RGB data are transferred for three clock cycles in 6-bit RGB interface. Data transferred, therefore, should be transferred in units of RGB. 4. Interface signals, VSYNC, HSYNC, DOTCLK, ENABLE and DB17-0 should be set in units of RGB (pixels) to match RGB transfer. 5. Transitions between internal operation mode and external display interface should follow the mode transition sequence shown below. 6. During the period between the completion of displaying one frame data and the next VSYNC signal, the display will remain front porch period.
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MDDI (MOBILE DISPLAY DIGITAL INTERFACE)
INTRODUCTION OF MDDI
The S6E63D6 supports MDDI. The MDDI is a differential & serial interface with high speed. Both command and image data transfer can be achieved with MDDI. MDDI host & client are linked with Data and STB line. Through Data line, command or image data is transferred from MDDI host to MDDI client, and vice versa. Data is transferred by packet unit. Through STB line, strobe signal is transferred. When the link is in "FORWARD direction", data is transferred from host to client; in "REVERSE direction", client transfer reverse data to MDDI host.
Forward Direction Reverse Direction
DATA+ DATADATA+ DATA-
STB+ STB-
STB+ STB-
Host GND Host Pwr
MDDI HOST
MDDI CLIENT
Figure60: Physical connection of MDDI host and client
DATA-STB ENCODING
Data is encoded using a DATA-STB method. DATA is carried over a bi-directional differential cable, while STB is carried over a unidirectional differential cable driven only by the host. Figure below illustrates how the data sequence "1110001011" is transmitted using DATA-STB encoding.
Figure61: Data-STB encoding The Following figure shows a sample circuit to generate DATA and STB from input data, and then recover the input data from DATA and STB. 97
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Figure62: Data / STB Generation & Recovery circuit
MDDI DATA / STB
The Data (MDP/MDN) and STB(MSP/MSN) signals are always operated in a differential mode to maximize noise immunity. Each differential pair is parallel-terminated with the characteristic impedance of the cable. All parallel-terminations are in the client device. Figure below illustrates the configuration of the drivers, receivers, and terminations. The driver of each signal pair has a differential current output. While receiving MDDI packets the MDDI_DATA and MDDI_STB pairs use a conventional differential receiver with a differential voltage threshold of zero volts. In the hibernation state the driver outputs are disabled and the parallel termination resistors pull the differential voltage on each signal pair to zero volts. During hibernation a special receiver on the MDDI_DATA pairs has an offset input differential voltage threshold of positive 125 mV, which causes the hibernation line receiver to interpret the un-driven signal pair as logic-zero level.
HOST
MDDI STB+ STB(host) Rterm MDDI STBEnable(host) MDDI DATA+ Data (host to client) MDDI DATAEnable(client) Rterm
CLIENT
VT = 0
STB(client)
VT = 0
Data (host to client)
Data (client to host)
VT = 0
Data (client to host)
wake-up (client to host)
VT = 125mV
VT = 125mV
wake-up (host to client)
Figure63: Differential connection between host and client
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HIBERNATION / WAKE-UP
S6E63D6 support hibernation mode for reducing interface power consumption. The MDDI link can enter the hibernation state quickly and wake up from hibernation quickly. This allows the system to force the MDDI link into hibernation frequently to reduce power consumption. In hibernation mode, hi-speed transceivers and receivers are disabled and low-speed & low-power receivers are enabled to detect wake-up sequence.
HOST
OFF
MDDI STB+ STB(host) Rterm MDDI STBEnable(host)
CLIENT
OFF VT = 0
STB(client)
OFF
MDDI DATA+ Data (host to client) MDDI DATARterm
OFF VT = 0
Data (host to client)
OFF
Data (client to host)
OFF
Enable(client)
VT = 0
Data (client to host)
ON
wake-up (client to host)
ON
VT = 125mV
wake-up (host to client)
VT = 125mV
Figure64: MDDI Transceiver / Receiver state in hibernation When the link wakes up from hibernation the host and client exchange a sequence of pulses. These pulses can be detect using low-speed, low-power receivers that consume only a fraction of the current of the differential receivers required to receive the signals at the maximum link operating speed. Both the client and the host can wake up the link, so 2-types of wake-up are supported in S6E63D6: Host-initiated link wakeup and Client-initiated link wakeup.
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MDDI LINK WAKE-UP PROCEDURE
Rules for Entering the Hibernation State : The host sends 64 MDDI_Stb cycles after the CRC of the Link Shutdown Packet. Also after this CRC the host shall drive MDDI_Data0 to a logic-zero level and disable the MDDI_Data0 output of the host in the range of after the rising edge of the 16th to before the rising edge of the 48th MDDI_Stb cycles (including output disable propagation delays). The host shall finish sending the 64 MDDI_Stb cycles after the CRC of the Link Shutdown packet before it initiates the wake-up sequence. The client shall wait until after the rigins edge of the 48th MDDI_Stb cycle after the CRC of the Link Shutdown Packet or later before it drives MDDI_Data0 to a logic-one level to attempt to wake-up the host. The client shall place its high-speed receivers for MDDI_Data0 and MDDI_Stb into hibernation any time after the rising edge of the 48th MDDI_Stb cycle after the CRC of the Link Shutdown Packet. It is recommended that the client place its high-speed MDDI_Data0 and MDDI_Stb receivers into hibernation before the rising edge of the 64th MDDI_Stb cycle after the CRC of the Link Shutdown Packet.
Rules for Wake-up from the Hibernation State : When the client needs service from the host it generates a request pulse by driving MDDI_Data0 to a logic-one level for 70 to 1000sec while MDDI_Stb is inactive and keeps MDDI_Data0 driven to a logic-one level for 70 MDDI_Stb cycles(range of 60 to 80) after MDDI_Stb becomes active. Then the client disables the MDDI_Data0 driver by placing it into a high-impedance state. If MDDI_Stb is active during hibernation(which is unlikely, but allowed per the spec) then the client may only drive MDDI_Data0 to a logic one level for 70 MDDI_Stb cycles (range of 60 to 80). This action causes the host to restart data traffic on the forward link and to poll the client for its status. The host shall detect the presence of the request pulse from the client (using the low-power differential receiver with a +125mV offset) and begin the startup sequence by first driving MDDI_Stb to a logic-zero level and MDDI_Data0 to a logic-high level for at least 200nsec, and then while toggling MDDI_Stb it shall continue to drive MDDI_Data0 to a logic-one level for 150 MDDI_Stb cycles (range of 140 to 160) and to logic-zero for 50 MDDI_Stb cycles. The client shall not send a service request pulse if it detects MDDI_Data0 at a logic-one level for more than 80 MDDI_Stb cycles. After the client has detected MDDI_Data0 at a logic-one level for 60 to80 MDDI_Stb cycles it shall begin to search for the interval where drives MDDI_Data0 to a logic-zero level for 50 MDDI_Stb cycles then the host starts sending packets on the link. The first packet sent shall be a Sub-frame Header Packet. The client begins to look for the Sub-frame header Packet after MDDI_Data0 is at a logic-zero level for 40 MDDI_Stb cycles of the 50 cycle interval. The host may initiate the wake-up by first enabling MDDI_Stb and simultaneously drive it to a logic-zero level. MDDI_Stb shall not be driven to a logic-one level until pulses are output as described below. After MDDI_Stb reaches a valid logic-zero level the host shall enable MDDI_Data0 and simultaneously drive it to a logic-one level. MDDI_Data0 shall not be driven to a logic-zero level during the wake-up process until the interval where it is 100
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driven to a logic-zero level for an interval of 50 MDDI_Stb pulses as described below. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level before driving pulses on MDDI_Stb. This timing relationship shall always occur while considering the worst-case output enable delays. This guarantees that the client has sufficient time to fully enable its MDDI_Stb receiver after being woken up by a logic-one level on MDDI_Data0 that was driven by the host.
Figure65: Process from entering Hibernation To exiting Hibernation
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1) Host-initiated Link Wake-up Procedure The simple case of a host-initiated wake-up is described below without contention from the client trying to wake up at the same time. The following sequence of events is illustrated in the following figure.
Figure66: Host-initiated link wakeup sequence The Detailed descriptions for labeled events are as follows: A. The host sends a Link Shutdown Packet to inform the client that the link will transition to the low-power hibernation state. B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host initially sets MDDI_Data0 to a logic-zero level, and then disables the MDDI_Data0 output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point C. C. The host enters the low-power hibernation state by disabling the MDDI_Data0 and MDDI_Stb drivers and by placing the host controller into a low-power hibernation state. It is also allowable for MDDI_Stb to be driven to logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state. D. After a while, the host begins the link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a valid logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. The client first detects the wake-up pulse using a low-power differential receiver having a +125mV input offset voltage. E. The host drivers are fully enabled and MDDI_Data0 is being driven to a logic-one level. The host begins to toggle MDDI_Stb in a manner consistent with having a logic-zero level on MDDI_Data0 for a duration of 150 MDDI_Stb cycles. F. The host drives MDDI_Data0 to logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb cycles. G. The host begins to transmit data on the forward link by sending a Sub-frame Header Packet. Beginning at point G the MDDI host generates MDDI_Stb based on the logic level on MDDI_Data0 so that proper data-strobe encoding commences from point G.
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Figure67: Host-initiated link wakeup sequence
2) Client-initiated Link Wake-up Procedure An example of a typical client-initiated service request event with no contention is illustrated in the following figure.
Figure68: Client-initiated link wake-up sequence The Detailed descriptions for labeled events are as follows: A. The host sends a Link Shutdown Packet to inform the client that the link will transition to the low-power hibernation state. B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host initially sets MDDI_Data0 to a logic-zero level, and then disables the MDDI_Data0 output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point C. C. The host enters the low-power hibernation state by disabling its MDDI_Data0 and MDDI_Stb driver outputs. It is also allowable for MDDI_Stb to be driven to logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state. D. After a while, the client begins the link restart sequence by enabling the MDDI_Stb receiver and also enabling an 103
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offset in its MDDI_Stb receiver to guarantee the state of the received version of MDDI_Stb is a logic-zero level in the client before the host enables its MDDI_Stb driver. The client will need to enable the offset in MDDI_Stb immediately before enabling its MDDI_Stb receiver to ensure that the MDDI_Stb receiver in the client is always receiving a valid differential signal and to prevent erroneous received signals from propagating into the client. After that, the client enables its MDDI_Data0 driver while driving MDDI_Data0 to a logic-one level. It is allowed for MDDI_Data0 and MDDI_Stb to be enabled simultaneously if the time to enable the offset and enable the standard MDDI_Stb differential receiver is less than 200 nsec. E. Within 1 msec the host recognizes the service request pulse, and the host begins the link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to a logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a valid fully-driven logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. F. The host begins outputting pulses on MDDI_Stb and shall keep MDDI_Data0 at a logic-one level for a total duration of 150 MDDI_Stb pulses through point H. The host generates MDDI_Stb in a manner consistent with sending a logic-zero level on MDDI_Data0. When the client recognizes the first pulse on MDDI_Stb it shall disable the offset in its MDDI_Stb receiver. G. The client continues to drive MDDI_Data0 to a logic-one level for 70 MDDI_Stb pulses, and the client disables its MDDI_Data0 driver at point G. The host continues to drive MDDI_Data0 to a logic-one level for duration of 80 additional MDDI_Stb pulses, and at point H drives MDDI_Data0 to logic-zero level. H. The host drives MDDI_Data0 to logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb cycles. I. After asserting MDDI_Data0 to logic-zero level and driving MDDI_Stb for duration of 50 MDDI_Stb pulses the host begins to transmit data on the forward link at point I by sending a Sub-frame Header Packet. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb cycles.
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Figure69: Client-initiated link wake-up sequence
S6E63D6 supports 2-types of client-initiated link wake-up: VSYNC based Link Wake-up & GPIO based Link Wake-up. As client-initiated wake-up action is executed in hibernation state only, register setting for each wake-up have to be set before link shut-down. VSYNC Based Link Wake-up In display-ON state, when the IC finishes displaying all internal GRAM data, data request must be transferred to MDDI host for new video data. As MDDI link is usually in hibernation for reducing interface power consumption, MDDI link wake-up must be done before internal GRAM update. In that case, client initiated link wake-up can be used as data request. 105
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When VSYNC based link wake-up register (50h: VWAKE_EN) is set, client initiated wake-up is executed in synchronization with the vertical-sync signal which generated in S6E63D6. Using VSYNC based link wake-up, tearing-less display can be accomplished if interface speed and wake-up time is well known. The following figure shows detailed timing for VSYNC based link wake-up.
SYNC STATE
A B
HIBERNATION STATE
WAKE-UP STATE
CD
SYNC STATE
EF
VWAKE_EN link_active frame_update client_wakeup
Figure70: VSYNC based link wake-up procedure The Detailed descriptions for labeled events are as follows: A. MDDI host writes to the VSYNC based link wakeup register to enable a wake-up based on internal vertical-sync signal. B. link_active goes low when the host puts in the link into hibernation after no more data needs to be sent to the S6E63D6. C. frame_update, the internal vertical-sync signal goes high indicating that update pointer has wrapped around and is now reading from the beginning of the frame buffer. Link wake-up point can be set using WKF and WKL (51h) registers. WKF specifies the number of frame before wake-up; WKL specifies the number of lines before wake-up. D. client_wakeup input to the MDDI client goes high to start the client initiated link wake-up. E. link_active goes high after the host brings the link out of hibernation. F. After link wake-up, client_wakeup signal and the VWAKE_EN register are cleared automatically. GPIO Based Link Wake-up In VSYNC-based link wake-up, wake-up enable register setting prior to link shut-down. GPIO based Link wake-up is enabled by interrupt from outside of the IC. For GPIO based link wake-up, GPIO interrupt enable and GPIO PAD mode (to input mode) setting must be set. Once S6E63D6 receive interrupt, internal GPIO base link wake-up flag set to high, and the following procedure is similar to that of VSYNC based link wake-up. The following figure shows detailed timing for GPIO based link wake-up.
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SYNC STATE
A B
HIBERNATION STATE
C
WAKE-UP STATE
DE
SYNC STATE
FG H
GPIO_EN link_active GPIO(input)* GPIO_INT* frame_update client_wakeup
Figure71: GPIO based link wake-up procedure The Detailed descriptions for labeled events are as follows: A. Host sets the GPIO interrupt enable register (69h: GPIO_EN) for a particular GPIO through register access packet. B. Link goes into hibernation (and link_active)goes low) when the host has no more data to send to the IC. C. GPIO input goes high, and the GPIO interrupt (GPIO_INT) is latched. D. Frame_update signal goes high indicating that the display has wrapped around. Link wake-up point can be set using WKF and WKL (51h) registers. E. Client_wakeup input to the MDDI client goes high to start the client initiated link wake-up. F. Link_active goes high after the host brings the link out of hibernation. G. After link wake-up, client_wakeup signal is reset to low. H. MDDI host clears the interrupt by writing to the interrupt clear register with the bit set for that particular interrupt (GPCLR: 68h). Between point G and H the host will have read the GPIO_INT values to see what interrupts are active.
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GPIO CONTROL
S6E63D6 offers 10(maximum) GPIO that can be used as input or output independently. Some application or device on the upper clamshell needs several control signals which are supplied by base band modem or application processor directly. If number of application on the upper clamshell increases, also control signals increase, causing the interface more costly. In S6E63D6, GPIO can be the solution for that problem. User may control the 10 GPIOs as input or output by use of simple register setting. So additional connection between base band modem / AP (application processor) and components on upper clamshell are not needed. The following table shows several set of register for GPIO. Register GPIO (66h) width Description Write [9:0] Read Write [9:0] Read Write [9:0] Read Write [9:0] Read Write [9:0] Read GPPOL (6Ah) register value. GPIO_EN (69h) register value. For GPIO input mode: GPIO interrupt polarity setting 10'h3FF GPIO_CON (67h) register value For GPIO input mode: clear specified GPIO interrupt (set by GPIO PAD input). GPIO interrupt state (set by GPIO PAD input). For GPIO input mode: enable specified GPIO interrupt 10'h000 For GPIO output mode: output GPIO register(66h) value to GPIO PAD GPIO PAD status GPIO PAD input/output mode control : (0 : input / 1 : output) 10'h000 Reset value
10'h000
GPIO_CON (67h)
GPCLR (68h)
10'h000
GPIO_EN (69h)
GPPOL (6Ah)
In GPIO output mode, the IC output GPIO (66h) register value to the defined PAD. Set GPIO_CON register as output mode before use GPIO output. 10 different GPIO output can be controlled simultaneously using 1-register access packet (66h register access) so that minimum access time for each GPIO output will be 1-register access time. GPIO input mode can only be used as client-initiated link wake-up. For more information, refer to GPIO based link wake-up section.
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3) Host-initiated Wake-up from Hibernation with Connection from client This is actually a host-initiated wake-up, but we have included the case where the client also wants to wake up the link with the latest possible request. The labeled events are : A. The host sends a Link Shutdown Packet to inform the client that the link will transition to the low-power hibernation state. B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host disables the MDDI_Data0 output in the range of 16 to 48 MDDI_Stb cycles(including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point C. C. The host enters the low-power hibernation state by disabling its MDDI_Data0 and MDDI_Stb driver outputs. It is also allowable for MDDI_Stb to be driven to a logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state. D. After a while, the host begins the link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to a logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a valid logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. E. The host drivers are fully enabled and MDDI_Data0 is being driven to a logic-one level. The host begins to toggle MDDI_Stb in a manner consistent with having a logic-zero level on MDDI_Data0 for a duration of 150 MDDI_Stb cycles. F. At up to 70 MDDI_Stb cycles after point E the client has not yet recognized that the host is driving MDDI_Data0 to a logic-one level so the client also drives MDDI_Data0 to a logic-one level. This occurs because the client has a need to request service from the host and does not recognize that the host has already begun the link restart sequence. G. The client ceases to drive MDDI_Data0, and places its driver into a high-impedance state by disabling its output. The host continues to drive MDDI_Data0 to a logic-one level for 80 additional MDDI_Stb cycles. H. The host drives MDDI_Data0 to a logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at a logic-zero level for 40 MDDI_Stb cycles. I. The host begins to transmit data on the forward link by sending a Sub-frame Header Packet. Beginning at point I the MDDI host generates MDDI_Stb based on the logic level on MDDI_Data0 so that proper data-strobe encoding commences from point I.
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Figure72: Host-initiated Wake-up process from Hibernation with Connection from client
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MDDI PACKET
MDDI transfer data by packet format. MDDI host can make many packets and transfer them. In S6E63D6, several packets format is supported. Most packets are transferred from MDDI host to client (forward direction); but reverse encapsulation packet is transferred from MDDI client to host (reverse direction). A number of packets, started by sub-frame header packet, construct 1 sub frame.
Figure73: MDDI packet structure Refer to MDDI packet structure, sub-frame header packet is placed in front of a sub-frame, and some sub-frame construct media-frame together. The following table describes 9 types of packet which is supported in S6E63D6.
PACKET Sub-frame header packet Register access packet Video stream packet Filler packet Reverse link encapsulation packet Round-trip delay measurement packet Client capability packet Clinet request and status packet Link shutdown packet FUNCTION Header of each sub frame Register setting Video data transfer Fill empty packet space Reverse data packet Host->client->host delay check Capability of client check Information about client status End of frame DIRECTION Forward Forward Forward Forward Reverse Forward/Reverse Reverse Reverse Forward
Sub-frame header packet
Figure74: Sub-frame header packet structure 111
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Preliminary
Register access packet
Figure75: Register access packet structure
Video Stream packet
Figure76: Video stream packet structure
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Preliminary
Filler packet
Figure77: Filler packet structure Link shutdown packet
Figure78: Link shutdown packet structure
: fixed value
For More information about MDDI packet, please refer to VESA MDDI spec.
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Preliminary MDDI OPERATING STATE
In MDDI, six operation modes are available. The following table describes six modes.
STATE SLEEP WAIT Normal NAP OSC ON ON ON ON Step-up Circuit Disabled Disabled Enabled Disabled Internal Logic status Display OFF MDDI Link hibernation Display OFF MDDI Link in SYNC Display ON MDDI Link in SYNC Display OFF MDDI Link in SYNC Display ON MDDI Link hibernation Display OFF MDDI Link OFF MDDI I/O Hibernation driver ON standard driver ON standard driver ON standard driver ON Wake-up by Host - Initiated Host - Initiated Client - Initiated (Vsync, GPIO) RESET
IDLE
ON
Enabled
Hibernation driver ON
STOP
OFF
Disabled
Driver All OFF
SLEEP: Initial status when external power is connected to the IC. In this state, internal oscillator is operating, and MDDI link is in hibernation state. As no command or signal is applied to the IC except RESET input, internal logic or step-up circuit is OFF. WAIT: After the wake-up sequence, the IC is in WAIT state. MDDI link is in SYNC, and internal logic or step-up is still OFF because no other register access or video stream packet is transferred to the IC. NORMAL: MDDI link, step-up circuit, and internal logic circuit is ON. Register access or Video data transfer is available in NORMAL state. IDLE: When no more video data update is needed, MDDI link is in hibernation so that interface power can be reduced. Internal step-up & logic circuits are still operating. MDDI link wakeup will be accomplished when vsync wakeup register is set before hibernation or GPIO interrupt is set. NAP: This state is set by register access. Step-up and Internal logic is OFF, but MDDI link is ON. MDDI link have to be in SYNC because the IC must receive commands for power save or normal operation STOP: STOP state is set by register access (R10h). In this state, MDDI link, internal oscillator, step-up, and logic circuit are all OFF. To release STOP state, input reset signal. After reset, status is SLEEP state.
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Preliminary
POWER ON
System power ON
System Reset input
SLEEP
- OSC : OSC ON - Step-up : Disabled - MDDI link : Hibernation - Logic : Display OFF
MDDI link synchronization procedure
WAIT
- OSC : OSC ON - Step-up : Disabled - MDDI link : in SYNC - Logic : Display OFF
1
NAP state set sequence 1) Display OFF sequence using register packet 2) NAP state setting(SLP=1) using register packet
1) Power setting using register packet 2) Step-up enable sequence using register packet 3) Frame buffer access using video packet 4) Display ON sequence using register packet
2
NAP state release sequence 1) NAP state register disable 2) Step-up enable sequence 3) Frame buffer update (optional) 4) Display ON sequence
NORMAL
- OSC : OSC ON - Step-up : Enabled - MDDI link : in SYNC - Logic : Display ON
D M IL D
3
IDLE state (when frame buffer update not needed) 1) Vsync wakeup enable register setting (optional) 2) Link shut-down using link shut-down packet (MDDI link is in hibernation state)
2
1
3
k in ak w ! up e-
NAP
IDLE
- OSC: OSC ON - Step-up: Disabled - MDDI link: in SYNC - Logic: Display OFF
- OSC: OSC ON - Step-up: Enabled - MDDI link:Hibernation - Logic: Display ON
- VSYNC wakeup - GPIO wakeup - Host initiated wakeup
- STOP state setting using register packet (both standard & offset receiver disabled)
STOP
Only RESET signal is admitted for wake-up from STOP state !
- OSC: OSC OFF - Step-up: Disabled - MDDI link:Link disabled - Logic: Display OFF
Figure79: Operating state in MDDI mode
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Preliminary
TEARING-LESS DISPLAY
In S6E63D6, the matching between data write timing and written data display timing is important. If timing is mismatched, tearing effect can occur. To avoid display tearing effect, two possible ways are suggested. First case is that data write is slower than speed of displaying written data. In this case, data write speed is not critical, but current consumption in interface will be increased because data transfer time is long. Data write time is selected widely (?) in this case. Other case is that data write is faster than speed of displaying written data. In this case, data update speed is very high so that transfer time is short. So current consumption in interface can be minimized, but it requires fast data transfer. The most important thing is to avoid data scan conflicts with data update. The following figures describe some examples to avoid display tearing phenomenon. . 1. Display speed is faster than data write.
Figure80: Tearing-less display: display speed is faster than data write 2. Display speed is slower than data write.
Figure81: Tearing-less display: data write speed is faster than display
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Preliminary SUB PANEL CONTROL
S6E63D6 support sub panel control function which controls sub panel driver IC using 80-mode protocol (CSB, RS, WRB & DB). When MDDI host (Base band modem) sends several packets to S6E63D6, if the packet is for sub panel, the IC converts the packet to 80-mode protocol & sends them to sub panel driver IC. So separated line for sub panel control are not needed. After all, S6E63D6 enables the sub panel driver IC which doesn't support MDDI to be applied to the system. S6E63D6 supports only 80-mode 18/16 bit format for sub panel control.
Main Panel (MDDl-Supported LDI) Sub Panel (Normal LDI)
TFT-LCD Module (SUB display) OLED Module (MAIN display)
LCD driver IC
LCD driver IC
80 mode Parallel I/F
MDDI
MDDI HOST
MDDI TRX/ RX
MSM (Baseband Modem)
Figure82: Schematic diagram of sub panel control function
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Preliminary
MAIN / SUB PANEL SELECTION
Using 7Ah register (7Ah address can be changed using SUB_SEL register), main / sub panel data path can be selected. When S6E63D6 receives register access packet (Initially 7Ah index) from MDDI host, it decodes the packet and checks the last bit of the register data field is `1' or `0'. If the last bit is `0', the following register access packet or video stream packet is transferred to the sub panel control signal generation block. Sub panel selection address (Initially 7Ah) can be changed using SUB_SEL register. Do not change the SUB_SEL value to previously occupied address.
Register Address = SUB_SEL
Register Data = 0000h
SUB panel Selection Procedure
Command Transfer (Register Access packet)
Command / Data transfer to Sub Panel driver IC (80-mode protocol)
Video Data Transfer (Video Stream packet)
Register Address = SUB_SEL
Register Data = 0001h
MAIN panel Selection Procedure Note: Initial value of SUB_SEL = 7Ah
Figure83: Main / Sub panel selection procedure When video data is transferred to the sub panel driver IC via S6E63D6, additional GRAM access command (normally 22h) is automatically generated in S6E63D6.
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Preliminary
SUB PANEL CONTROL TIMING
1. TFT type sub panel timing 1.1 Register data transfer timing
If sub panel is selected, and sub panel type is TFT, register setting is executed like below figure. Register data is transferred through S_DB[17:10] & S_DB[8:1] in 18/16 bit type. If 9/8 bit type is used, data is transferred thorough S_DB[17:10]. Refer to sub panel control(15h index) section.
1 Register Access Packet MDDI Data Stream
Header Register Address C R C Register Data C R C
(0007h)
(030Fh)
S_DB[17:0]
0000Eh
(index 07h)
00C1Eh
(030Fh 16bit data)
S_CSB S_RS S_WRB index write parameter write
Figure84: 18/16 bit type register access data transfer In 9/8 bit mode, S_DB[17:10] is used. In this mode, data is transferred at two times. First transfer is MSB 8bit and second transfer is LSB 8bit.
1 Register Access Packet MDDI Data Stream
Header Register Address C R C Register Data C R C
(0007h)
(030Fh)
S_DB[17:10]
00h
(MSB 8bit)
07h
(LSB 8bit)
03h
(MSB 8bit)
0Fh
(LSB 8bit)
S_CSB S_RS S_WRB index write parameter write
Figure85: 9/8 bit type register access data transfer
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Preliminary
This figure shows register setting in 18/16 bit & 68 mode. In 68 mode, S_WRB must be connected to E_RDB of sub panel module. RW_WRB of sub panel module must be tied to VSS. Because S6E63D6 only writes data to sub panel
module.
1 Register Access Packet MDDI Data Stream
Header Register Address C R C Register Data C R C
(0007h)
(030Fh)
S_DB[17:0]
0000Eh
(index 07h)
00C1Eh
(030Fh 16bit data)
S_CSB S_RS S_WRB index write parameter write
Figure86: 68 mode 18 bit register data transfer
1.2 Video data transfer timing
In TFT type sub panel, STN_EN register in 15h index is "0", and if user wants to use 68-mode interface protocol, then MPU_MODE is set to "1". 18/16/9/8 mode is selected as setting SUB_IM register. Refer to 15h index description. This figure shows 80 mode 18 bit Video data transfer.
1 Video Stream Packet(18-bpp)
MDDI Data Stream
Header
C R C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(01ABCh)
(100FFh)
(0FF00h)
(000FFh)
(00001h)
C R C
DB[17:0]
(data output to sub LDI)
00044h
GRAM write enable (index 22h)
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
01ABCh
100FFh
0FF00h
000FFh
00001h
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
GRAM Write Enable (22h index)
pixel write
pixel write
pixel write
pixel write
pixel write
Figure87: 80 mode 18 bit video data transfer
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Preliminary
This fugure shows 68 mode 18 bit. In 68 mode, S_WRB must be connected to E_RDB of sub panel module. RW_WRB of sub panel module must be tied to VSS. Because S6E63D6 only writes data to sub panel module.
Figure88: 68 mode 18 bit video data transfer
This figure shows 80-mode 16 bit Video data transfer.
1 Video Stream Packet(16-bpp)
MDDI Data Stream
Header
C R C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(1ABCh)
(00FFh)
(FF00h)
(01FFh)
(0001h)
C R C
DB[17:10],[8:1]
(data output to sub LDI)
00022h
GRAM write enable (index 22h)
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
1ABCh
00FFh
FF00h
01FFh
0001h
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
GRAM Write Enable (22h index)
pixel write
pixel write
pixel write
pixel write
pixel write
Figure89: 80 mode 16 bit video data transfer
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Preliminary
This figure shows 80-mode 9 bit Video data transfer.
1 Video Stream Packet(18-bpp)
MDDI Data Stream
Header
C R C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(01ABCh)
(100FFh)
(0FF00h)
(000FFh)
(00001h)
C R C
DB[17:9]
(data output to sub LDI)
044h
044h
00Dh
MSB
0BCh
LSB
080h
MSB
0FFh
LSB
07Fh
MSB
100h
LSB
000h
MSB
0FFh
LSB
000h
MSB
001h
LSB
GRAM write enable
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
GRAM Write Enable (22h index)
pixel write
pixel write
pixel write
pixel write
pixel write
Figure90: 80 mode 9 bit video data transfer
This figure shows 80-mode 8 bit Video data transfer.
1 Video Stream Packet(16-bpp)
MDDI Data Stream
Header
C R C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(1ABCh)
(00FFh)
(FF00h)
(01FFh)
(0001h)
C R C
DB[17:10]
(data output to sub LDI)
22h
22h
1Ah
MSB
BCh
LSB
00h
MSB
FFh
LSB
FFh
MSB
00h
LSB
01h
MSB
FFh
LSB
00h
MSB
01h
LSB
GRAM write enable
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
GRAM Write Enable (22h index)
pixel write
pixel write
pixel write
pixel write
pixel write
Figure91: 80 mode 8 bit video data transfer
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Preliminary
2. STN type sub panel timing 2.1 Register data transfer timing
This figure shows conventional type STN mode register data setting. Conventional type does not include parameter. Instruction type is only 8bit. To use STN type, STN_EN is set to "1". In STN type, S6E63D6 controls S_RS pin using register address[0] in register access packet. Register address[0] is "0", then S_RS is set to "0", and register address[0] is "1", S_RS is set to "1". Refer to sub panel control(15h index) section.
1 Register Access Packet MDDI Data Stream
Header Register Address C R C Register Data C R C Header Register Address C R C Register Data C R C
(0000h)
(0055h)
(0000h)
(0001h)
S_DB[17:0]
000AAh (55h index)
00002h (0001h parameter)
S_CSB S_RS S_WRB index write parameter write
Figure92: 80 mode STN type convetional register instruction
This type is used to include parameter. When instruction is transferred, S_RS is zero, and when parameter is transferred, S_RS is "1". S_RS is controlled using register address[0] of register access packet.
1 Register Access Packet MDDI Data Stream
Header Register Address C R C Register Data C R C Header Register Address C R C Register Data C R C
(0000h)
(0055h)
(0001h)
(0001h)
S_DB[17:0]
000AAh (55h index)
00002h (0001h parameter)
S_CSB S_RS S_WRB index write parameter write (RS = 1)
Figure93: 80 mode STN type included parameter
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Preliminary
2.2 Video data transfer timing
In STN mode, video data start register (like 22H is TFT mode) does not need generally. But some STN type needs video data start register. If those type STN DDI is used, user has to set the register index. This figure shows STN 16 bit mode video data transfer.
1 Video Stream Packet(18-bpp)
MDDI Data Stream
Header
C R C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(01ABCh)
(100FFh)
(0FF00h)
(000FFh)
(00001h)
C R C
DB[17:0]
(data output to sub LDI)
00044h
(write disabled)
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
01ABCh
100FFh
0FF00h
000FFh
00001h
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
pixel write
pixel write
pixel write
pixel write
pixel write
Figure94: 80 mode STN type 16 bit video data transfer
This figure shows STN 8bit mode video data transfer. If STN video data is 16bit mode, data transfer is executed during 2 times. Fist transfer is MSB 8bits, and second is LSB 8bits.
1 Video Stream Packet(16-bpp)
MDDI Data Stream
Header
C R C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(1ABCh)
(00FFh)
(FF00h)
(01FFh)
(0001h)
C R C
DB[17:10]
(data output to sub LDI)
22h
22h
1Ah
MSB
BCh
LSB
00h
MSB
FFh
LSB
FFh
MSB
00h
LSB
01h
MSB
FFh
LSB
00h
MSB
01h
LSB
22h write disabled
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
pixel write
pixel write
pixel write
pixel write
pixel write
Figure95: 80 mode STN type video data transfer
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Preliminary
SUB PANEL CONTROL TIMING
1. Index/parameter write for sub panel LDI
2. Image data write for sub panel LDI
3. Change data path from sub panel to main panel
mddi_rxbyte_ena pixel_data(internal) S_CSB S_RS S_WRB DB
data3
data4
data5
data6
data7
data8
data9
data1
data2
data3
data4
data5
data6
data7
data8
data9
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Preliminary
AMOLED PANEL CONTROL INTERFACE S6E63D6 outputs some timing signals (FLM, SFTCLK, SFTCLKB, SCLK1, SCLK2, CLA, CLB, CLC, BICTL_L, BICTL_R, EX_FLM, EX_CLK, EX_CLKB, ESR) for controlling an AMOLED panel with built-in gates. S6E63D6 has built-in level shifter for AMOLED panel. Output voltage level for high is VGH voltage, for low is VGL voltage.
Figure96: An Exemplary Combination
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Preliminary
PANEL INTERFACE TIMING
Figure97: Timing Diagram of Panel Interface Signals (GTCON=00)
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Preliminary
In Internal Clock Operation mode, the panel interface signals are generated based on internally generated oscillator clock. But in External Clock Operation mode, those are generated based on RGB I/F Signals. The Figure below shows the relation between them for External Clock Operation mode.
Figure98: VSYNC and Panel Interface Signals in External Clock Operation mode
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Preliminary R, G, B INDEPENDENT GAMMA ADJUSTMENT FUNCTION
S6E63D6 provides the gamma adjustment function to display 262,144 colors simultaneously. The gamma adjustment is executed by the amplitude adjusting registers and curve adjusting registers. Since, those control registers incorporate independent adjustment of the gamma function for R, G, B independently, it is highly possible that user determine the best appropriate configuration according to the trait of the display panel.
Figure99: Grayscale Control
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Preliminary
STRUCTURE of GRAYSCALER
Grayscale level can be determined by registers that adjust both amplitude and curve. Also, the period of each level is split by the internal ladder resistor and generates level between V0 to V63. Amplitude adjusting part determines upper (V0) and lower (V63) bound voltage and curve adjusting part determines each 4 point (V4, V10, V21, V42) voltages independently for flexible curve control.
Figure100: Structure of gray scaler
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Preliminary
R, G, B INDEPENDENT GAMMA ADJUSTMENT REGISTERS
These are registers to set up the grayscale voltage in accordance with the gamma specification of the AMOLED panel. The registers can set up both amplitude and curve character of grayscale voltage respectively with corresponding bits as the function of grayscale number. Each configuration can be made for R, G, B independently. There shows the operation of each register below.
Grqy Scale Voltage
V0
Gray Scale Data a) Top level control (4bit : 16step)
V63
Gray Scale Voltage
V0
Gray Scale Data b) Bottom level control (7bit : 128step)
V63
Gray Scale Voltage
VREG1OUT
Gray Scale Data
V63
Flexible curve by 4 point control (6bits: 64step)
Amplitude adjustment
Curve adjustment
Figure101: The Operation of Adjusting Register
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Preliminary
AMPLITUDE ADJUSTING REGISTERS These are the registers for adjusting the amplitude of grayscale voltage. The registers for adjusting amplitude consists of two parts, one of which is for top level voltage (V0) and the other of which is for bottom level voltage (V63). CR0[3:0], CG0[3:0] and CB0[3:0] registers control the top level voltage. CR5[6:0], CG5[6:0] and CB5[6:0] registers control the bottom level voltage. V0 and V63 are selected in divided voltage from ladder resistor strings between VGS and VREG1OUT. Separate registers are prepared for R, G, B respectively. Table52: Amplitude adjusting register Content of configuration for G for B CG0[3:0] CG5[6:0] CB0[3:0] CB5[6:0] Grayscale voltage adjusting for top level voltage Grayscale voltage adjusting for bottom level voltage
Register R40H ~ R41H
for R CR0[3:0] CR5[6:0]
Table53: Relationship between amplitude adjusting register and V0 Register value Formula CR0[3:0], CG0[3:], CB0[3:0] 0000 VREG1OUT - VREG1OUT x ( 0 /105) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VREG1OUT - VREG1OUT x ( 1 / 105) VREG1OUT - VREG1OUT x ( 2 / 105) VREG1OUT - VREG1OUT x ( 3 / 105) VREG1OUT - VREG1OUT x ( 4 / 105) VREG1OUT - VREG1OUT x ( 5 / 105) VREG1OUT - VREG1OUT x ( 6 / 105) VREG1OUT - VREG1OUT x ( 7 / 105) VREG1OUT - VREG1OUT x ( 8 / 105) VREG1OUT - VREG1OUT x ( 9 / 105) VREG1OUT - VREG1OUT x ( 10 / 105) VREG1OUT - VREG1OUT x ( 11 / 105) VREG1OUT - VREG1OUT x ( 12 / 105) VREG1OUT - VREG1OUT x ( 13 / 105) VREG1OUT - VREG1OUT x ( 14 / 105) VREG1OUT - VREG1OUT x ( 15 / 105)
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Preliminary
Table54: Relation between amplitude adjusting register and V63 Register value Formula CR5[6:0] CG5[[6:0], CB5[6:0] 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 . . . 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 VREG1OUT - VREG1OUT x ( 35 / 210) VREG1OUT - VREG1OUT x ( 36 / 210) VREG1OUT - VREG1OUT x ( 37 / 210) VREG1OUT - VREG1OUT x ( 38 / 210) VREG1OUT - VREG1OUT x ( 39 / 210) VREG1OUT - VREG1OUT x ( 40 / 210) VREG1OUT - VREG1OUT x ( 41 / 210) VREG1OUT - VREG1OUT x ( 42 / 210) VREG1OUT - VREG1OUT x ( 43 / 210) . . . VREG1OUT - VREG1OUT x (147 / 210) VREG1OUT - VREG1OUT x (148 / 210) VREG1OUT - VREG1OUT x (149 / 210) VREG1OUT - VREG1OUT x (150 / 210) VREG1OUT - VREG1OUT x (151 / 210) VREG1OUT - VREG1OUT x (152 / 210) VREG1OUT - VREG1OUT x (153 / 210) VREG1OUT - VREG1OUT x (154 / 210) VREG1OUT - VREG1OUT x (155 / 210) VREG1OUT - VREG1OUT x (156 / 210) VREG1OUT - VREG1OUT x (157 / 210) VREG1OUT - VREG1OUT x (158 / 210) VREG1OUT - VREG1OUT x (159 / 210) VREG1OUT - VREG1OUT x (160 / 210) VREG1OUT - VREG1OUT x (161 / 210) VREG1OUT - VREG1OUT x (162 / 210)
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Preliminary
CURVE ADJUSTING REGISTERS The curve adjusting registers are used for adjusting the characteristic curve of the grayscale voltage as the function of grayscale number. The registers also control R, G, B independently like the amplitude adjusting register. To accomplish the adjustment, these registers control the each 4 reference voltage by three 47 to 1 selector and a 64 to 1 selector. The 47 or 64 leveled reference voltage generated from the ladder resistor strings between V0 and V63. The registers for adjusting curve consist of 4 reference point - V4, V10, V21 and V42. Table55: Gamma Curve Adjusting Register Content of configuration for G for B CG1[5:0] CG2[5:0] CG3[5:0] CG4[5:0] CB1[5:0] CB2[5:0] CB3[5:0] CB4[5:0] Grayscale voltage adjusting for V4 Grayscale voltage adjusting for V10 Grayscale voltage adjusting for V21 Grayscale voltage adjusting for V42
Register
For R CR1[5:0] CR2[5:0] CR3[5:0] CR4[5:0]
R43H ~ R46H
CR1[5:0], CG1[5:0], CB1[5:0] Regis ter Control for V 4
CR2[5:0], CG2[5:0], CB2[5:0] Regis ter Control for V 10
Grayscale voltage
Gray s cale data
Grayscale voltage
Gray s cale data
CR3[5:0], CG3[5:0], CB3[5:0] Regis ter Control for V 21
CR4[5:0], CG4[5:0], CB4[5:0] Regis ter Control for V 42
Grayscale voltage
Gray s cale data
Grayscale voltage
Gray s cale data
Figure102: Gamma curve adjustment
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
CURVE ADJUSTING BLOCK Below appears the table indicating the relation between the value of these registers and voltage-dividing ratio. Table56: Relationship between value of curve adjusting register and voltage-dividing ratio Register value CR1[5:0] CG1[5:0] CB1[5:0] 000000 000001 000010 000011 000100 . . . 111011 111100 111101 111110 111111 CR3[5:0] CG3[5:0] CB3[5:0] 000000 000001 000010 000011 000100 . . . 101010 101011 101100 101101 101110 ~ 111111 Voltage dividing resistor value V4 formula V0 - (V0 - V10) x 98/210 V0 - (V0 - V10) x 99/210 V0 - (V0 - V10) x 100/210 V0 - (V0 - V10) x 101/210 V0 - (V0 - V10) x 102/210 . . . V0 - (V0 - V10) x 157/210 V0 - (V0 - V10) x 158/210 V0 - (V0 - V10) x 159/210 V0 - (V0 - V21) x 160/210 V0 - (V0 - V21) x 161/210 V21 formula V0 - (V0 - V42) x 85/150 V0 - (V0 - V42) x 86/150 V0 - (V0 - V42) x 87/150 V0 - (V0 - V42) x 88/150 V0 - (V0 - V42) x 89/150 . . . V0 - (V0 - V42) x 127/150 V0 - (V0 - V42) x 128/150 V0 - (V0 - V42) x 129/150 V0 - (V0 - V42) x 130/150 V0 - (V0 - V42) x 131/150 Register value CR2[5:0] CG2[5:0] CB2[5:0] 000000 000001 000010 000011 000100 . . . 101010 101011 101100 101101 101110 ~ 111111 CR4[5:0] CG4[5:0] CB4[5:0] 000000 000001 000010 000011 000100 . . . 101010 101011 101100 101101 101110 ~ 111111 Voltage dividing resistor value V10 formula V0 - (V0 - V21) x 193/300 V0 - (V0 - V21) x 194/300 V0 - (V0 - V21) x 195/300 V0 - (V0 - V21) x 196/300 V0 - (V0 - V21) x 197/300 . . . V0 - (V0 - V21) x 235/300 V0 - (V0 - V21) x 236/300 V0 - (V0 - V21) x 237/300 V0 - (V0 - V21) x 238/300 V0 - (V0 - V21) x 239/300 V42 formula V0 - (V0 - V63) x 95/150 V0 - (V0 - V63) x 96/150 V0 - (V0 - V63) x 97/150 V0 - (V0 - V63) x 98/150 V0 - (V0 - V63) x 99/150 . . . V0 - (V0 - V63) x 137/150 V0 - (V0 - V63) x 138/150 V0 - (V0 - V63) x 139/150 V0 - (V0 - V63) x 140/150 V0 - (V0 - V63) x 141/150
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
64 GRAY SCALE OUTPUT VOLTAGE Below appears the table indicating the relation between the GRAM data value and output voltage value. Table57: Grayscale Output Voltage Formula Output value Gray data V0 V4 + ( V0 - V4 ) x 28/48 V4 + ( V0 - V4 ) x 12/48 V4 + ( V0 - V4 ) x 6/48 V4 V10 + ( V4 - V10 ) x 20/25 V10 + ( V4 - V10 ) x 15/25 V10 + ( V4 - V10 ) x 10/25 V10 + ( V4 - V10 ) x 7/25 V10 + ( V4 - V10 ) x 3/25 V10 V21 + ( V10 - V21 ) x 21/24 V21 + ( V10 - V21 ) x 19/24 V21 + ( V10 - V21 ) x 17/24 V21 + ( V10 - V21 ) x 14/24 V21 + ( V10 - V21 ) x 12/24 V21 + ( V10 - V21 ) x 10/24 V21 + ( V10 - V21 ) x 8/24 V21 + ( V10 - V21 ) x 6/24 V21 + ( V10 - V21 ) x 4/24 V21 + ( V10 - V21 ) x 2/24 V21 V42 + ( V21 - V42 ) x 20/21 V42 + ( V21 - V42 ) x 19/21 V42 + ( V21 - V42 ) x 18/21 V42 + ( V21 - V42 ) x 17/21 V42 + ( V21 - V42 ) x 16/21 V42 + ( V21 - V42 ) x 15/21 V42 + ( V21 - V42 ) x 14/21 V42 + ( V21 - V42 ) x 13/21 V42 + ( V21 - V42 ) x 12/21 V42 + ( V21 - V42 ) x 11/21 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Gray date 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Output value
V42 + ( V21 - V42 ) x 10/21 V42 + ( V21 - V42 ) x 9/21 V42 + ( V21 - V42 ) x 8/21 V42 + ( V21 - V42 ) x 7/21 V42 + ( V21 - V42 ) x 6/21 V42 + ( V21 - V42 ) x 5/21 V42 + ( V21 - V42 ) x 4/21 V42 + ( V21 - V42 ) x 3/21 V42 + ( V21 - V42 ) x 2/21 V42 + ( V21 - V42 ) x 1/21 V42 V63 + ( V42 - V63) x 20/21 V63 + ( V42 - V63) x 19/21 V63 + ( V42 - V63) x 18/21 V63 + ( V42 - V63) x 17/21 V63 + ( V42 - V63) x 16/21 V63 + ( V42 - V63) x 15/21 V63 + ( V42 - V63) x 14/21 V63 + ( V42 - V63) x 13/21 V63 + ( V42 - V63) x 12/21 V63 + ( V42 - V63) x 11/21 V63 + ( V42 - V63) x 10/21 V63 + ( V42 - V63) x 9/21 V63 + ( V42 - V63) x 8/21 V63 + ( V42 - V63) x 7/21 V63 + ( V42 - V63) x 6/21 V63 + ( V42 - V63) x 5/21 V63 + ( V42 - V63) x 4/21 V63 + ( V42 - V63) x 3/21 V63 + ( V42 - V63) x 2/21 V63 + ( V42 - V63) x 1/21 V63
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
OUTPUT LEVEL AS THE FUNCTION OF GRAM DATA Output level could be described as the function of GRAM DATA like below.
V0
REV = 1
Output Level
V63
000000
REV = 0
111111
RAM data (Independently controlable characteristics to RGB)
Figure103: Relationship between RAM Data and Output Voltage
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GRAM data RGB 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Grayscale REV=0 REV=1 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V63 V62 V61 V60 V59 V58 V57 V56 V55 V54 V53 V52 V51 V50 V49 V48 Table58: GRAM Data and Grayscale Level GRAM data Grayscale GRAM data Grayscale RGB 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 REV=0 REV=1 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V47 V46 V45 V44 V43 V42 V41 V40 V39 V38 V37 V36 V35 V34 V33 V32 RGB 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 REV=0 REV=1 V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V31 V30 V29 V28 V27 V26 V25 V24 V23 V22 V21 V20 V19 V18 V17 V16 GRAM data RGB 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Grayscale REV=0 REV=1 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
THE 8-COLOR DISPLAY MODE The S6E63D6 incorporates 8-color display mode. The voltage levels to be used are VREG1OUT and V63 and all the other grayscale levels V0~V62are halt. So that it attempts to lower power consumption. During the 8-color mode, the Gamma micro adjustment register, C1R~C4R, C1G~C4G and C1B~C4B are invalid. The level power supply (V0-V62) is in OFF condition during the 8-color mode in order to select VREG1OUT/V63.
Figure104: 8-color display control
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary SET UP FLOW OF STANDBY
Figure105: Setup flow of STNADBY
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary OSCILLATION CIRCUIT
The S6E63D6 can provide R-C oscillation. S6E63D6 internal oscillator does not need to attach the external resistor. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the oscillator frequency control register setting. Since R-C oscillation stops during the standby mode, power consumption can be reduced.
FRAME FREQUENCY CALCULATION
The relation between the AMOLED driver duty and the frame frequency can be found by the following expression.
Figure106: Formula for the Frame Frequency EXAMPLE CALCULATION Parameters Line Number Frame Frequency BP FP fosc Description 320 60 8 8 1,290,240 Hz
Display Clock Frequency Table59: DISPLAY CLOCK FREQUENCY 1 HCLK 1 Horizontal Period Internal Clock Operation External Clock Operation Fosc / 2 Fdotclk / 8(RIM=00,01) Fdotclk/24(RIM = 10) 32 HCLKs 32 HCLKs
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary APPLICATION CIRCUIT
The following figure indicates a typical application circuit for S6E63D6.
Figure107: S6E63D6 Application (80 System CPU Parallel Interface)
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table60: Absolute Maximum Rating (VSS = 0V)
Item
Supply voltage Supply voltage for step-up circuit Supply Voltage range Input Voltage range
Symbol
VDD3 VCI |VLIN2 - VLIN3| Vin
Rating
-0.3 ~ 5.0 -0.3 ~ 5.0 20 -0.3 to VDD + 0.5
Unit
V V V V
Notes:
1. Absolute maximum rating is the limit value. When the IC is exposed operating environment beyond this range, the IC do not assure operations and may be damaged permanently, not be able to be recovered. 2. Absolute maximum rating is guaranteed only when our company's package used.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DC CHARACTERISTICS
Table61: DC Characteristics (VSS = 0V)
Characteristic
Driving voltage Photo Sensor Power Logic Operating Voltage Operating frequency 1st step-up input voltage 1st step-up output voltage 1st step-up output efficiency 2nd step-up output voltage 2nd step-up output efficiency 3rd step-up output voltage 3 step-up output efficiency Source Output voltage deviation (channel to channel) Output voltage deviation (Chip to Chip) Source driver output voltage range LTPS driver output voltage deviation Driving voltage
rd
Symbol
VGH VGL VINT VSP RVDD fosc VCI1 VLOUT1 VLOUT1 VLOUT2 VLOUT2 VLOUT3 VLOUT3
CONDITION
Frame frequency = 60Hz Display line = 320 line Without load I_VLOUT1_LOAD = 2.3mA Without load I_VLOUT2_LOAD = 0.1mA Without load I_VLOUT3_LOAD = 0.1mA
MIN
4.6 -7.8 -4.0 2.9 1.45 1192.3 2.1 +4.2 90 +6.3 90 -11.0 90
TYP
3.0 1.5 1324.8 95 93 93 TBD TBD -
MAX
6.6 -5.0 -1.0 3.1 1.55 1457.2 2.75 +5.5 +11.0 -6.3 -
Unit
V V V V V kHz V V % V % V %
Note
-
-
-
-
mV
Vso dVGH dVGL
voltage deviation
0.96 -
4.2 TBD TBD TBD TBD TBD
mV V V V V uA mA -
Current consumption during normal operation
IVDD3 IVCI
No load, Ta = 25 C VCI=2.8V Frame(f)=60Hz
-
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Characteristic
Power Supply Voltage Power Supply Voltage Logic High level input voltage Logic Low level input voltage Logic High level output voltage Logic Low level output voltage Analog High level output voltage Analog Low level output voltage
Symbol
VCI VDD3 VIH VIL VOH VOL EL_ONOH EL_ONOL
CONDITION
Operating Voltage I/O supply Voltage
MIN
2.5 1.65 0.7*VDD3 0.0
TYP
2.8 1.8
MAX
3.3 3.3 VDD3 0.3*VDD3 VDD3 0.2*VDD3
Unit
Note
V V V V V V V
IOUT = -1mA IOUT = +1mA 8uA 8uA
0.8*VDD3 0.0 1.6 0
0.4
V
(VDD3 = 1.65~3.3V, VCI = 2.5~3.3V, Ta = 25)
Characteristic Symbol CONDITION MIN TYP MAX Unit Note
VREG1OUT
.
4.185
4.2
4.215
V
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PANEL INTERFACE GATE IC LESS LEVEL SHIFTER OUTPUT CHARACTERISTICS
Figure108: AC Characteristics of Level Shifter Output
Figure109: LTPS Signal Load Test Point
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table62: AC Parameters of Level Shifter Outputs
Total Load R(ohm)
BICTL CLA, CLB, CLC FLM SFTCLK, SFTCLKB SCLK1, SCLK2 EX_FLM EX_CLK, EX_CLKB ESR 1320 3500 900 895 895 910 910 1320
Level Shifter Output High Level
VGH VGH VGH VGH VGH VGH VGH VGH
C(pF)
78 39 42 61 61 42 68 60
Low Level
VGL VGL VGL VGL VGL VGL VGL VGL
Item
Rising Time Falling Time Rising Time Falling Time Rising Time Falling Time Rising Time Falling Time Cross Point Rising Time Falling Time Rising Time Falling Time Rising Time Falling Time Cross Point Rising Time Falling Time
Symbol
tr tf tr tf tr tf tr tf rCross tr tf tr tf tr tf rCross tr tf
Min
40 40 -
Typ
50 50 -
Max
2000 2000 500 500 1000 1000 300 300 60 300 300 1000 1000 350 350 60 2000 2000
Unit
ns ns ns ns ns ns ns ns % ns ns ns ns ns ns % ns ns
SOURCE OUTPUT
tDD
Certain Grayscale Voltage mV
S1 ~ S240
Certain Grayscale Voltage mV
Figure110: AC Characteristics of Source Driver Output Table63: AC Parameters of Source Driver Output Test Condition Value VCI1 = 2.75 V Fosc = 1324.8 kHz 9 usec / 4V max. Grayscale to be reached = 10mV (with demux) Load Resistance R = 32 Kohm Load Capacitance C = 20pF SAP[2:0]=101
Symbol
tDD
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
VINT Source - Functions and conditions of VINT output - During 1H(=51.2us, 1 horizontal line) time, turn on Tr to reset Cst for about 10us - Peak current = 3.15mA - VINT ripple(at saturation position) < 100mV - VINT Saturation time < 7us
Figure111: Current Wave of VINT
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
AC CHARACTERISTICS
Table64: Parallel Write Interface Characteristics (68 Mode) (VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC)
Specification Characteristic
Cycle time Pulse rise / fall time Write Read Write Pulse width high Read RS,RW to CSB, E setup time Pulse width low RS,RW to CSB, E hold time CSB to E time Write data setup time Write data hold time Read data delay time Read data hold time Write Read
Symbol Min.
tCYCW68 tCYCR68 tR, tF tWHW68 tWHR68 tWLW68 tWLR68 tAS68 tAH68 tCW68 tWDS68 tWDH68 tRDD68 tRDH68 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Unit Max.
TBD TBD TBD
ns
Figure112: AC Characteristics (68 Mode) 149
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table65: Parallel Write Interface Characteristics (80 Mode) (VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC)
Specification Characteristic
Cycle time Pulse rise / fall time Pulse width low Pulse width high Write Read Write Read Write Read
Symbol Min.
tCYCW80 tCYCR80 tR, tF tWLW80 tWLR80 tWHW80 tWHR80 tAS80 tAH80 tcw80 tWDS80 tWDH80 tRDD80 tRDH80 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Unit Max.
TBD TBD TBD ns
RS to CSB, WRB(RDB) setup time RS to CSB, WRB(RDB) hold time CSB to WRB(RDB) time Write data setup time Write data hold time Read data delay time Read data hold time
Figure113: AC Characteristics (80 Mode) 150
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table66: Clock Synchronized Serial Write Mode Characteristics (VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC)
specification Characteristic
Serial clock write cycle time Serial clock read cycle time Serial clock rise / fall time Pulse width high for write Pulse width high for read Pulse width low for write Pulse width low for read Chip Select setup time Chip Select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time
Symbol Min.
tscyc tscyc tR, tF tSCHW tSCHR tSCLW tSCLR tCSS tCSH tSIDS tSIDH tSODD tSODH TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Unit Max.
TBD TBD ns ns ns ns ns ns ns ns ns ns ns ns ns
Transfer Start
Transfer End
VIH
CSB
VIL
tscyc tCSS
VIH
tR
VIH VIL VIL
tSCHW / tSCHR
tF
VIH
tSCLW / tSCLR VIH VIL VIL
tCSH
SCL
tSIDS
VIH
tSIDH
VIH
SDI
VIL
INPUT DATA
VIL
INPUT DATA
tSODH
tSODD
VOH1
SDO
OUTPUT DATA
VOL1
OUTPUT DATA
VOH1 VOL1
Figure114: AC Characteristics (SPI Mode)
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table67: RGB Data Interface Characteristics (VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC)
18/16bit RGB interface Characteristic
DOTCLK cycle time DOTCLK rise / fall time DOTCLK Pulse width high DOTCLK Pulse width low Vertical Sync Setup Time Vertical Sync Hold Time Horizontal Sync Setup Time Horizontal Sync Hold Time ENABLE setup time ENABLE hold time PD data setup time PD data hold time HSYNC-ENABLE Time VSYNC-HSYNC Time
6bit RGB interface Min.
TBD TBD TBD TBD TBD TBD TBD
Unit
Symbol Min.
tDCYC tR, tF tDCHW tDCLW tvsys tvsyh thsys thsyh tENS tENH tPDS tPDH tHE thv TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD HBP TBD
Max.
TBD -
Max.
TBD ns
TBD TBD TBD TBD TBD TBD
HBP TBD tDCYC
Note : HBP is Horizontal Back-porch.
(When VSPL=0, HSPL=0, DPL=0, EPL=1) Figure115: AC Characteristics (RGB Interface Mode)
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
RESET TIMING
tRES
RESETB
VIL VIL
Note : Reset low pulse width shorter than 10us do not make reset. It means undesired short pulse such as glitch, bouncing noise or electrostatic discharge do not cause irregular system reset. Please refer to the table below. Figure116: AC characteristics (RESET timing)
Parameter tRES
Description Reset low pulse width
Min 10
Max -
Unit us
Table68: Reset Operation regarding tRES Pulse Width
tRES Pulse
Shorter than 5 us Longer than 10 us Between 5 us and 10 us
Action
No reset Reset Not determined
1. User may or may not use RESETB pin. In order to use it, user should satisfy the conditions described in the above tables. But when not wants to use RESETB, user may fix this pin to VDD3 level because internally generated POR (Power-On-Reset) is used. 2. Spike Rejection also applies during a valid reset pulse as shown below:
10us Reset is accepted
20ns
Less than 20ns width positive spike will be rejected.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
EXTERNAL POWER ON / OFF SEQUENCE
VDD3 must be applied earlier than VCI or at least applied simultaneously with VCI. When regulator cap is 1F, RESETB must be applied after VCI have been applied. The applied time gap between VCI and RESETB is minimum 1ms. As regulator cap becomes larger, this time gap must be increased. Otherwise function is not guaranteed.
Figure117: External power on sequence b) EXTERNAL POWER OFF SEQUENCE VDD3 must be powered down later than VCI or at least powered down simultaneously with VCI. VCI must be powered down after RESETB have been powered down. The time gap of powered down between RESETB and VCI is minimum 1ms. Otherwise function is not guaranteed.
Figure118: External Power Off sequence
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
NOTICE
Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. 2. Always test and inspect products under the environment with no penetration of light.
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